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1. general description the saf1760 is a hi-speed universal serial bus (usb) host controller with a generic processor interface. it integrates one enhanced host controller interface (ehci), one transaction translator (tt) and three transceivers. the host controller portion of the saf1760 and the three transceivers comply to ref . 1 univ ersal ser ial bus speci? cation re v . 2.0 . the ehci portion of the saf1760 is adapted from ref . 2 enhanced host controller interf ace speci? cation f or univ ersal ser ial bus re v . 1.0 . the integrated high-performance hi-speed usb transceivers enable the saf1760 to handle all hi-speed usb transfer speed modes: high-speed (480 mbit/s), full-speed (12 mbit/s) and low-speed (1.5 mbit/s). the three downstream ports allow simultaneous connection of three devices at different speeds (high-speed, full-speed and low-speed). the generic processor interface allows the saf1760 to be connected to various processors as a memory-mapped resource. the saf1760 is a slave host: it does not require bus-mastering capabilities of the host system bus. the interface can be con?gured, ensuring compatibility with a variety of processors. data transfer can be performed on 16 bits or 32 bits, using programmed input/output (pio) or direct memory access (dma) with major control signals con?gurable as active low or active high. integration of the tt allows connection to full-speed and low-speed devices, without the need of integrating open host controller interface (ohci) or universal host controller interface (uhci). instead of dealing with two sets of software drivers, ehci and ohci or uhci, you need to deal with only one set, ehci, that dramatically reduces software complexity and ic cost. 2. features n automotive quali?ed in accordance with aec-q100 n the host controller portion of the saf1760 complies with ref . 1 univ ersal ser ial bus speci? cation re v . 2.0 n the ehci portion of the saf1760 is adapted from ref . 2 enhanced host controller interf ace speci? cation f or univ ersal ser ial bus re v . 1.0 n contains three integrated hi-speed usb transceivers that support high-speed, full-speed and low-speed modes n integrates a tt for original usb (full-speed and low-speed) device support n up to 64 kb internal memory (8 k 64 bit) accessible through a generic processor interface; operation in multitasking environments is made possible by the implementation of virtual segmentation mechanism with bank switching on task request saf1760 hi-speed universal serial bus host controller for embedded applications rev. 01 9 november 2009 product data sheet
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 2 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller n generic processor interface, non-multiplexed and variable latency, with a con?gurable 32-bit or 16-bit external data bus; the processor interface can be de?ned as variable-latency or sram type (memory mapping) n slave dma support to reduce the load of the host system cpu during the data transfer to or from the memory n integrated phase-locked loop (pll) with a 12 mhz crystal or an external clock input n integrated multi-con?guration fifo n optimized msec-based or multi-msec-based proprietary transfer descriptor (ptd) interrupt n tolerant i/o for low voltage cpu interface (1.65 v to 3.6 v) n 3.3 v-to-5.0 v external power supply input n integrated 5.0 v-to-1.8 v or 3.3 v-to-1.8 v voltage regulator (internal 1.8 v for low-power core) n internal power-on reset and low-voltage reset n supports suspend and remote wake-up n target current consumption: u normal operation; one port in high-speed active: i cc < 100 ma u suspend mode: i cc(susp) < 150 m a at room temperature n built-in con?gurable overcurrent circuitry (digital or analog overcurrent protection) 3. applications the saf1760 can be used to implement a hi-speed usb compliant host controller connected to most of the cpus present in the market today, having a generic processor interface with de-multiplexed address and data bus. this is because of the ef?cient slave-type interface of the saf1760. the internal architecture of the saf1760 is such that it can be used in a large spectrum of applications requiring a high-performance internal host controller. 3.1 examples of a multitude of possible applications n automotive integrated head unit: for connectivity ports n set-top box: for connecting external high-performance mass storage devices n mobile phone: for connecting various usb devices n personal digital assistant (pda): for connecting a large variety of usb devices n printer: for connecting external memory card readers, allowing direct printing n digital still camera (dsc): for printing to an external usb printer, for direct printing n mass storage: for connecting external memory card readers or other mass storage devices, for direct back-up n the low power consumption and deep power management modes of the saf1760 make it particularly suitable for use in portable devices.
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 3 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 4. ordering information table 1. ordering information type number package name description version SAF1760BE lqfp128 plastic low pro?le quad ?at package; 128 leads; body 14 20 1.4 mm sot425-1
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 4 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 5. block diagram all ground pins should normally be connected to a common ground plane. fig 1. block diagram risc processor interface: memory management unit + slave dma controller + interrupt control memory arbiter and fifo ehci and operational registers pie transaction translator and ram port routing or control logic + host and hub port status hi-speed usb atx1 dp1 dm1 psw1_n oc1_n psw3_n oc3_n 001aai632 pll 30 mhz 60 mhz xtal1 global control and power management power-on reset and v bat on digital and analog overcurrent detection reset_n suspend/ wakeup_n ref5v a[17:1] generic processor bus hc payload memory (60 kb) 5 v-to-1.8 v voltage regulator 16-bit or 32-bit hc ptd memory (3 kb) + hardware configuration registers v cc(5v0) usb full-speed and low-speed data path usb high-speed data path hi-speed usb atx2 hi-speed usb atx3 dp2 dm2 dp3 dm3 37 to 39, 41 to 43, 45 to 47, 49, 51, 52, 54, 56 to 58, 60 to 62, 64 to 66, 68 to 70, 72 to 74, 76 to 78, 80 82, 84, 86, 87, 89, 91 to 93, 95 to 98, 100 to 103, 105 106 cs_n 107 rd_n 108 wr_n 114 dreq 116 dack 112 irq 10, 40, 48, 59, 67, 75, 83, 94, 104, 115 xtal2 11 12 clkin 13 2 20 18 27 25 21 127 19 gnda 26 gnda 28 128 34 33 gnda 35 1 rref1 16 gnd (rref1) 15 rref2 23 gnd (rref2) 22 rref3 30 gnd (rref3) 29 122 119 bat_on_n 110 5 v-to-3.3 v voltage regulator reg3v3 reg1v8 5, 50, 85, 118 9 6, 7 gndd 4, 17, 24, 31, 123 data[15:0]/data[31:0] SAF1760BE psw2_n oc2_n v cc(i/o) 17 32 8 gnd(osc) 14, 36, 44, 55, 63, 71, 79, 90, 99, 109 gnda 53, 88, 121 gndc
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 5 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 6. pinning information 6.1 pinning 6.2 pin description fig 2. pin con?guration (lqfp128); top view SAF1760BE 102 39 64 128 103 65 1 38 001aai633 table 2. pin description symbol [1] [2] pin type [3] description lqfp128 oc3_n 1 ai port 3 analog (5 v input) and digital overcurrent input; if not used, connect to v cc(i/o) through a 10 k w resistor input, 5 v tolerant ref5v 2 ai 5 v reference input for analog oc detector; connect a 100 nf decoupling capacitor test1 3 i connect to ground gnda 4 g analog ground reg1v8 5 p core power output (1.8 v); internal 1.8 v for the digital core; used for decoupling; connect a 100 nf capacitor; for details on additional capacitor placement, see section 7.8 v cc(5v0) 6 p input to internal regulators (3.0 v to 5.5 v); connect a 100 nf decoupling capacitor; see section 7.8 v cc(5v0) 7 p input to internal regulators (3.0 v to 5.5 v); connect a 100 nf decoupling capacitor; see section 7.8 gnd(osc) 8 g oscillator ground reg3v3 9 p regulator output (3.3 v); for decoupling only; connect a 100 nf capacitor and a 4.7 m f-to-10 m f capacitor; see section 7.8 v cc(i/o) 10 p digital supply voltage; 1.65 v to 3.6 v; connect a 100 nf decoupling capacitor; see section 7.8 xtal1 11 ai 12 mhz crystal connection input; connect to ground if an external clock is used; see t ab le 89 xtal2 12 ao 12 mhz crystal connection output
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 6 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller clkin 13 i 12 mhz oscillator or clock input; when not in use, connect to v cc(i/o) gndd 14 g digital ground gnd(rref1) 15 g rref1 ground rref1 16 ai reference resistor connection; connect a 12 k w 1 % resistor between this pin and the rref1 ground gnda [4] 17 g analog ground dm1 18 ai/o downstream data minus port 1 gnda 19 g analog ground dp1 20 ai/o downstream data plus port 1 psw1_n 21 od power switch port 1, active low output pad, push-pull open-drain, 8 ma output drive, 5 v tolerant gnd(rref2) 22 g rref2 ground rref2 23 ai reference resistor connection; connect a 12 k w 1 % resistor between this pin and the rref2 ground gnda [5] 24 g analog ground dm2 25 ai/o downstream data minus port 2 gnda 26 g analog ground dp2 27 ai/o downstream data plus port 2 psw2_n 28 od power switch port 2, active low output pad, push-pull open-drain, 8 ma output drive, 5 v tolerant gnd(rref3) 29 g rref3 ground rref3 30 ai reference resistor connection; connect a 12 k w 1 % resistor between this pin and the rref3 ground gnda [6] 31 g analog ground dm3 32 ai/o downstream data minus port 3 gnda 33 g analog ground dp3 34 ai/o downstream data plus port 3 psw3_n 35 od power switch port 3, active low output pad, push-pull open-drain, 8 ma output drive, 5 v tolerant gndd 36 g digital ground data0 37 i/o data bit 0 input and output bidirectional pad, push-pull input, 3-state output, 4 ma output drive, 3.3 v tolerant data1 38 i/o data bit 1 input and output bidirectional pad, push-pull input, 3-state output, 4 ma output drive, 3.3 v tolerant data2 39 i/o data bit 2 input and output bidirectional pad, push-pull input, 3-state output, 4 ma output drive, 3.3 v tolerant table 2. pin description continued symbol [1] [2] pin type [3] description lqfp128
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 7 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller v cc(i/o) 40 p digital supply voltage; 1.65 v to 3.6 v; connect a 100 nf decoupling capacitor; see section 7.8 data3 41 i/o data bit 3 input and output bidirectional pad, push-pull input, 3-state output, 4 ma output drive, 3.3 v tolerant data4 42 i/o data bit 4 input and output bidirectional pad, push-pull input, 3-state output, 4 ma output drive, 3.3 v tolerant data5 43 i/o data bit 5 input and output bidirectional pad, push-pull input, 3-state output, 4 ma output drive, 3.3 v tolerant gndd 44 g digital ground data6 45 i/o data bit 6 input and output bidirectional pad, push-pull input, 3-state output, 4 ma output drive, 3.3 v tolerant data7 46 i/o data bit 7 input and output bidirectional pad, push-pull input, 3-state output, 4 ma output drive, 3.3 v tolerant data8 47 i/o data bit 8 input and output bidirectional pad, push-pull input, 3-state output, 4 ma output drive, 3.3 v tolerant v cc(i/o) 48 p digital supply voltage; 1.65 v to 3.6 v; connect a 100 nf decoupling capacitor; see section 7.8 data9 49 i/o data bit 9 input and output bidirectional pad, push-pull input, 3-state output, 4 ma output drive, 3.3 v tolerant reg1v8 50 p core power output (1.8 v); internal 1.8 v for the digital core; used for decoupling; connect a 100 nf capacitor; for details on additional capacitor placement, see section 7.8 data10 51 i/o data bit 10 input and output bidirectional pad, push-pull input, 3-state output, 4 ma output drive, 3.3 v tolerant data11 52 i/o data bit 11 input and output bidirectional pad, push-pull input, 3-state output, 4 ma output drive, 3.3 v tolerant gndc 53 g core ground data12 54 i/o data bit 12 input and output bidirectional pad, push-pull input, 3-state output, 4 ma output drive, 3.3 v tolerant gndd 55 g digital ground data13 56 i/o data bit 13 input and output bidirectional pad, push-pull input, 3-state output, 4 ma output drive, 3.3 v tolerant table 2. pin description continued symbol [1] [2] pin type [3] description lqfp128
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 8 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller data14 57 i/o data bit 14 input and output bidirectional pad, push-pull input, 3-state output, 4 ma output drive, 3.3 v tolerant data15 58 i/o data bit 15 input and output bidirectional pad, push-pull input, 3-state output, 4 ma output drive, 3.3 v tolerant v cc(i/o) 59 p digital supply voltage; 1.65 v to 3.6 v; connect a 100 nf decoupling capacitor; see section 7.8 data16 60 i/o data bit 16 input and output bidirectional pad, push-pull input, 3-state output, 4 ma output drive, 3.3 v tolerant data17 61 i/o data bit 17 input and output bidirectional pad, push-pull input, 3-state output, 4 ma output drive, 3.3 v tolerant data18 62 i/o data bit 18 input and output bidirectional pad, push-pull input, 3-state output, 4 ma output drive, 3.3 v tolerant gndd 63 g digital ground data19 64 i/o data bit 19 input and output bidirectional pad, push-pull input, 3-state output, 4 ma output drive, 3.3 v tolerant data20 65 i/o data bit 20 input and output bidirectional pad, push-pull input, 3-state output, 4 ma output drive, 3.3 v tolerant data21 66 i/o data bit 21 input and output bidirectional pad, push-pull input, 3-state output, 4 ma output drive, 3.3 v tolerant v cc(i/o) 67 p digital supply voltage; 1.65 v to 3.6 v; connect a 100 nf decoupling capacitor; see section 7.8 data22 68 i/o data bit 22 input and output bidirectional pad, push-pull input, 3-state output, 4 ma output drive, 3.3 v tolerant data23 69 i/o data bit 23 input and output bidirectional pad, push-pull input, 3-state output, 4 ma output drive, 3.3 v tolerant data24 70 i/o data bit 24 input and output bidirectional pad, push-pull input, 3-state output, 4 ma output drive, 3.3 v tolerant gndd 71 g digital ground data25 72 i/o data bit 25 input and output bidirectional pad, push-pull input, 3-state output, 4 ma output drive, 3.3 v tolerant data26 73 i/o data bit 26 input and output bidirectional pad, push-pull input, 3-state output, 4 ma output drive, 3.3 v tolerant table 2. pin description continued symbol [1] [2] pin type [3] description lqfp128
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 9 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller data27 74 i/o data bit 27 input and output bidirectional pad, push-pull input, 3-state output, 4 ma output drive, 3.3 v tolerant v cc(i/o) 75 p digital supply voltage; 1.65 v to 3.6 v; connect a 100 nf decoupling capacitor; see section 7.8 data28 76 i/o data bit 28 input and output bidirectional pad, push-pull input, 3-state output, 4 ma output drive, 3.3 v tolerant data29 77 i/o data bit 29 input and output bidirectional pad, push-pull input, 3-state output, 4 ma output drive, 3.3 v tolerant data30 78 i/o data bit 30 input and output bidirectional pad, push-pull input, 3-state output, 4 ma output drive, 3.3 v tolerant gndd 79 g digital ground data31 80 i/o data bit 31 input and output bidirectional pad, push-pull input, 3-state output, 4 ma output drive, 3.3 v tolerant test2 81 g connect to ground a1 82 i address pin 1 input, 3.3 v tolerant v cc(i/o) 83 p digital supply voltage; 1.65 v to 3.6 v; connect a 100 nf decoupling capacitor; see section 7.8 a2 84 i address pin 2 input, 3.3 v tolerant reg1v8 85 p core power output (1.8 v); internal 1.8 v for the digital core; used for decoupling; connect a 100 nf capacitor and a 4.7 m f-to-10 m f capacitor; see section 7.8 a3 86 i address pin 3 input, 3.3 v tolerant a4 87 i address pin 4 input, 3.3 v tolerant gndc 88 g core ground a5 89 i address pin 5 input, 3.3 v tolerant gndd 90 g digital ground a6 91 i address pin 6 input, 3.3 v tolerant a7 92 i address pin 7 input, 3.3 v tolerant a8 93 i address pin 8 input, 3.3 v tolerant table 2. pin description continued symbol [1] [2] pin type [3] description lqfp128
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 10 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller v cc(i/o) 94 p digital supply voltage; 1.65 v to 3.6 v; connect a 100 nf decoupling capacitor; see section 7.8 a9 95 i address pin 9 input, 3.3 v tolerant a10 96 i address pin 10 input, 3.3 v tolerant a11 97 i address pin 11 input, 3.3 v tolerant a12 98 i address pin 12 input, 3.3 v tolerant gndd 99 g digital ground a13 100 i address pin 13 input, 3.3 v tolerant a14 101 i address pin 14 input, 3.3 v tolerant a15 102 i address pin 15 input, 3.3 v tolerant a16 103 i address pin 16 input, 3.3 v tolerant v cc(i/o) 104 p digital supply voltage; 1.65 v to 3.6 v; connect a 100 nf decoupling capacitor; see section 7.8 a17 105 i address pin 17 input, 3.3 v tolerant cs_n 106 i chip select signal assertion indicates the saf1760 being accessed; active low input, 3.3 v tolerant rd_n 107 i read enable; active low input, 3.3 v tolerant wr_n 108 i write enable; active low input, 3.3 v tolerant gndd 109 g digital ground bat_on_n 110 od to indicate the presence of a minimum 3.3 v on pins 6 and 7 (open-drain); connect to v cc(i/o) through a 10 k w pull-up resistor output pad, push-pull open-drain, 8 ma output drive, 5 v tolerant n.c. 111 nc not connected irq 112 o host controller interrupt signal output pad, 4 ma drive, 3.3 v tolerant n.c. 113 nc not connected dreq 114 o dma controller request for the host controller output pad, 4 ma drive, 3.3 v tolerant table 2. pin description continued symbol [1] [2] pin type [3] description lqfp128
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 11 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller [1] symbol names ending with underscore n, for example, name_n, represent active low signals. [2] all ground pins should normally be connected to a common ground plane. [3] i = input only; o = output only; i/o = digital input/output; od = open-drain output; ai/o = analog input/output; ai = analog input; p = power; g = ground supply; nc = not connected. [4] for port 1. [5] for port 2. [6] for port 3. v cc(i/o) 115 p digital supply voltage; 1.65 v to 3.6 v; connect a 100 nf decoupling capacitor; see section 7.8 dack 116 i host controller dma request acknowledgment; when not in use, connect to v cc(i/o) through a 10 k w pull-up resistor input, 3.3 v tolerant test3 117 i connect to v cc(i/o) through a 10 k w pull-up resistor reg1v8 118 p core power output (1.8 v); internal 1.8 v for the digital core; used for decoupling; connect a 100 nf capacitor; for details on additional capacitor placement, see section 7.8 suspend/ wakeup_n 119 i/od host controller suspend and wake-up; 3-state suspend output (active low) and wake-up input circuits are connected together ? high = output is 3-state; saf1760 is in suspend mode ? low = output is low; saf1760 is not in suspend mode connect to v cc(i/o) through an external 10 k w pull-up resistor output pad, open-drain, 4 ma output drive, 3.3 v tolerant test4 120 i pull up to v cc(i/o) gndc 121 g core ground reset_n 122 i external power-up reset; active low; when reset is asserted, it is expected that bus signals are idle, that is, not toggling input, 3.3 v tolerant remark: during reset, ensure that all the input pins to the saf1760 are not toggling and are in their inactive states. gnda 123 g analog ground test5 124 ai/o connect a 220 nf capacitor between this pin and pin 125 test6 125 ai/o connect a 220 nf capacitor between this pin and pin 124 test7 126 i connect to 3.3 v oc1_n 127 ai port 1 analog (5 v input) and digital overcurrent input; if not used, connect to v cc(i/o) through a 10 k w resistor input, 5 v tolerant oc2_n 128 ai port 2 analog (5 v input) and digital overcurrent input; if not used, connect to v cc(i/o) through a 10 k w resistor input, 5 v tolerant table 2. pin description continued symbol [1] [2] pin type [3] description lqfp128
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 12 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 7. functional description 7.1 saf1760 internal architecture: advanced nxp slave host controller and hub the ehci block and the hi-speed usb hub block are the main components of the advanced nxp slave host controller. the ehci is the latest generation design, with improved data bandwidth. the ehci in the saf1760 is adapted from ref . 2 enhanced host controller interf ace speci? cation f or univ ersal ser ial bus re v . 1.0 . the internal hi-speed usb hub block replaces the companion host controller block used in the original architecture of a pci hi-speed usb host controllers to handle full-speed and low-speed modes. the hardware architecture in the saf1760 is simpli?ed to help reduce cost and development time, by eliminating the additional work involved in implementing the ohci software required to support full-speed and low-speed modes. figure 3 shows the internal architecture of the saf1760. the saf1760 implements the ehci that has an internal port, the root hub port (not available externally), on which the internal hub is connected. the three external ports are always routed to the internal hub. the internal hub is a hi-speed usb (usb 2.0) hub including the tt. remark: the root hub must be enabled and the internal hub must be enumerated. enumerate the internal hub as if it is externally connected. at the host controller reset and initialization, the internal root hub port will be polled until a new connection is detected, showing the connection of the internal hub. the internal hi-speed usb hub is enumerated using a sequence similar to a standard hi-speed usb hub enumeration sequence, and the polling on the root hub is stopped because the internal hi-speed usb hub will never be disconnected. when enumerated, the internal hub will report the three externally available ports.
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 13 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 7.1.1 internal clock scheme and port selection the saf1760 has three ports. figure 4 shows the internal clock scheme of the saf1760. figure 4 shows that the host clock is derived from port 2. port 2 does not need to be enabled by software, if only port 1 or port 3 is used. no port needs to be disabled by external pull-up resistors, if not used. the dp and dm of the unused ports need not be externally pulled high because there are internal pull-down resistors on each port that are enabled by default. t ab le 3 lists the various port connection scenarios. fig 3. internal hub 004aaa513 ehci root hub internal hub (tt) external ports enumeration and polling using actual ptds portsc1 port3 port1 port2 fig 4. saf1760 clock scheme 004aaa535 host core digital core port 2 atx port 1 atx port 3 atx xosc host clock: 48 mhz, 30 mhz, 60 mhz pll 12 mhz in
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 14 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 7.2 host controller buffer memory block 7.2.1 general considerations the internal addressable host controller buffer memory is 63 kb. the 63 kb effective memory size is the result of subtracting the size of the registers (1 kb) from the total addressable memory space de?ned in the saf1760 (64 kb). this is the optimized value to achieve the highest performance with minimal cost. the saf1760 is a slave host controller. this means that it does not need access to the local bus of the system to transfer data from the system memory to the saf1760 internal memory, unlike the case of the original pci hi-speed usb host controllers. therefore, correct data must be transferred to both the ptd area and the payload area by pio (using cpu access) or programmed dma. the slave-host architecture ensures better compatibility with most of the processors present in the market today because not all processors allow a bus-master on the local bus. it also allows better load balancing of the processors local bus because only the internal bus arbiter of the processor controls the transfer of data dedicated to usb. this prevents the local bus from being busy when other more important transfers may be in the queue; and therefore achieving a linear system data ?ow that has less impact on other processes running at the same time. the considerations mentioned are also the main reason for implementing the pre-fetching technique, instead of using a ready signal. the resulting architecture avoids freezing of the local bus, by asserting ready, enhancing the saf1760 memory access time, and avoiding introduction of programmed additional wait states. for details, see section 7.3 and section 8.3.8 . the total amount of memory allocated to the payload determines the maximum transfer size speci?ed by a ptd, a larger internal memory size results in less cpu interruption for transfer programming. this means less time spent in context switching, resulting in better cpu usage. table 3. port connection scenarios port con?guration port 1 port 2 port 3 one port (port 1) dp and dm are routed to usb connector dp and dm are not connected (left open) dp and dm are not connected (left open) one port (port 2) dp and dm are not connected (left open) dp and dm are routed to usb connector dp and dm are not connected (left open) one port (port 3) dp and dm are not connected (left open) dp and dm are not connected (left open) dp and dm are routed to usb connector two ports (ports 1 and 2) dp and dm are routed to usb connector dp and dm are routed to usb connector dp and dm are not connected (left open) two ports (ports 2 and 3) dp and dm are not connected (left open) dp and dm are routed to usb connector dp and dm are routed to usb connector two ports (ports 1 and 3) dp and dm are routed to usb connector dp and dm are not connected (left open) dp and dm are routed to usb connector three ports (ports 1, 2 and 3) dp and dm are routed to usb connector dp and dm are routed to usb connector dp and dm are routed to usb connector
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 15 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller a larger buffer also implies a larger amount of data can be transferred. the transfer, however, can be done over a longer period of time, to maintain the overall system performance. each transfer of the usb data on the usb bus can span for up to a few milliseconds before requiring further cpu intervention for data movement. the internal architecture of the saf1760 allows a ?exible de?nition of the memory buffer for optimization of the data transfer on the cpu extension bus and the usb. it is possible to implement various data transfer schemes, depending on the number and type of usb devices present. for example: push-pull; data can be written to half of the memory while data in the other half is being accessed by the host controller and sent on the usb bus. this is useful especially when a high-bandwidth continuous or periodic data ?ow is required. through an analysis of the hardware and software environment regarding the usual data ?ow and performance requirements of most embedded systems, nxp has determined the optimal size for the internal buffer as approximately 64 kb. 7.2.2 structure of the saf1760 host controller memory the 63 kb internal memory consists of the ptd area and the payload area. ptd memory zone is divided into three dedicated areas for each main type of usb transfer: isochronous (iso), interrupt (int) and asynchronous transfer list (atl). as shown in t ab le 4 , the ptd areas for iso, int and atl are grouped at the beginning of the memory, occupying the address range 0400h to 0fffh, following the register address space. the payload or data area occupies the next memory address range 1000h to ffffh, meaning that 60 kb of memory are allocated for the payload data. a maximum of 32 ptd areas and their allocated payload areas can be de?ned for each type of transfer. the structure of a ptd is similar for every transfer type and consists of eight double words (dws) that must be correctly programmed for a correct usb data transfer. the reserved bits of a ptd must be set to logic 0. a detailed description of the ptd structure can be found in section 9 . the transfer size speci?ed by the ptd determines the contiguous usb data transfer that can be performed without any cpu intervention. the respective payload memory area must be equal to the transfer size de?ned. the maximum transfer size is ?exible and can be optimized, depending on the number and nature of usb devices or ptds de?ned and their respective maxpacketsize. the cpu will program the dma to transfer the necessary data in the payload memory. the next cpu intervention will be required only when the current transfer is completed and dma programming is necessary to transfer the next data payload. this is normally signaled by the irq that is generated by the saf1760 on completing the current ptd, meaning all the data in the payload area was sent on the usb bus. the external irq signal is asserted according to the settings in the irq mask or or irq mask and registers, see section 8.4 . the ram is structured in blocks of ptds and payloads so that while the usb is executing on an active transfer-based ptd, the processor can simultaneously ?ll up another block area in the ram. a ptd and its payload can then be updated on-the-?y without stopping or delaying any other usb transaction or corrupting the ram data.
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 16 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller some of the design features are: ? the address range of the internal ram buffer is from 0400h to ffffh. ? the internal memory contains isochronous, interrupt and asynchronous ptds, and respective de?ned payloads. ? all accesses to the internal memory are double word aligned. ? internal memory address range calculation: memory address = (cpu address - 0400h) (shift right >> 3). base address is 0400h. table 4. memory address memory map cpu address memory address iso 0400h to 07ffh 0000h to 007fh int 0800h to 0bffh 0080h to 00ffh atl 0c00h to 0fffh 0100h to 017fh payload 1000h to ffffh 0180h to 1fffh fig 5. memory segmentation and access block diagram 004aaa436 ptd1 ptd2 ptd32 ptd1 ptd2 . . . . ptd32 payload payload 63 kb usb bus usb high-speed host and transaction translator (full-speed and low-speed) interrupt async payload ptd32 . . ptd1 ptd2 isochronous memory mapped input/output, memory management unit, slave dma controller and interrupt control registers arbiter control signals 240 mb/s address data (64 bits) d[15:0]/d[31:0] a[17:1] . . . . . . . . cs_n rd_n wr_n dreq dack irq micro- processor
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 17 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller both the cpu interface logic and the usb host controller require access to the internal saf1760 ram at the same time. the internal arbiter controls these accesses to the internal memory, organized internally on a 64-bit data bus width, allowing a maximum bandwidth of 240 mb/s. this bandwidth avoids any bottleneck on accesses both from the cpu interface and the internal usb host controller. 7.3 accessing the saf1760 host controller memory: pio and dma the cpu interface of the saf1760 can be con?gured for a 16-bit or 32-bit data bus width. when the saf1760 is con?gured for a 16-bit data bus width, the upper unused 16 data lines must be pulled up to v cc(i/o) . this can be achieved by connecting data[31:16] lines together to a single 10 k w pull-up resistor. the 16-bit or 32-bit data bus width con?guration is done by programming bit 8 of the hw mode control register. this will determine the register and memory access types in both pio and dma modes. all accesses must be word-aligned for 16-bit mode and double word aligned for 32-bit mode, where one word = 16 bits. when accessing the host controller registers in 16-bit mode, the register access must always be completed using two subsequent accesses. in the case of a dma transfer, the 16-bit or 32-bit data bus width con?guration will determine the number of bursts that will complete a certain transfer length. in pio mode, cs_n, wr_n and rd_n are used to access registers and memory. in dma mode, the data validation is performed by dack, instead of cs_n, together with the wr_n and rd_n signals. the dreq signal will always be asserted as soon as the saf1760 dma is enabled. 7.3.1 pio mode access, memory read cycle the following method has been implemented to reduce the read access timing in the case of a memory read: ? the memory register contains the starting address and the bank selection to read from the memory. before every new read cycle of the same or different banks, an appropriate value is written to this register. ? once a value is written to this register, the address is stored in the fifo of that bank and is then used to pre-fetch data for the memory read of that bank. for every subsequent read operation executed at a contiguous address, the address pointer corresponding to that bank is automatically incremented to pre-fetch the next data to be sent to the cpu. memory read accesses for multiple banks can be interleaved. the fifo block handles the multiplexing of appropriate data to the cpu. ? the address written to the memory register is incremented and used to successively pre-fetch data from the memory irrespective of the value on the address bus for each bank, until a new value for a bank is written to the memory register. this is valid only when the address refers to the memory space (400h to ffffh). for example, consider the following sequence of operations: C write the starting (read) address 4000h and bank1 = 01b to the memory register. when rd_n is asserted for three cycles with a[17:16] = 01b, the returned data corresponds to addresses 4000h, 4004h and 4008h.
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 18 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller remark: once 4000h is written to the memory register for bank1, the bank select value determines the successive incremental addresses used to fetch data. that is, the fetching of data is independent of the address on a[15:0] lines. C write the starting (read) address 4100h and bank2 = 10b to the memory register. when rd_n is asserted for four cycles with a[17:16] = 10b, the returned data corresponds to addresses 4100h, 4104h, 4108h and 410ch. consequently, the rd_n assertion with a[17:16] = 01b will return data from 400ch because the bank1 read stopped there in the previous cycle. also, rd_n assertions with a[17:16] = 10b will now return data from 4110h because the bank2 read stopped there in the previous cycle. 7.3.2 pio mode access, memory write cycle the pio memory writes access is similar to a normal memory access. it is not necessary to set the pre-fetching address before a write cycle to the memory. the saf1760 internal write address will not be automatically incremented during consecutive write accesses; unlike in a series of saf1760 memory read cycles. the memory write address must be incremented before every access. 7.3.3 pio mode access, register read cycle the pio register read access is similar to a general register access. it is not necessary to set a pre-fetching address before a register read. the saf1760 register read address will not be automatically incremented during consecutive read accesses; unlike in a series of saf1760 memory read cycles. the saf1760 register read address must be correctly speci?ed before every access. 7.3.4 pio mode access, register write cycle the pio register write access is similar to a general register access. it is not necessary to set a pre-fetching address before a register write. the saf1760 register write address will not be automatically incremented during consecutive write accesses; unlike in a series of saf1760 memory read cycles. the saf1760 register write address must be correctly speci?ed before every access. 7.3.5 dma mode, read and write operations the internal saf1760 host controller dma is a slave dma. the host system processor or dma must ensure the data transfer to or from the saf1760 memory. the saf1760 dma supports a dma burst length of 1, 4, 8 and 16 cycles for both the 16-bit and 32-bit data bus width. dreq will be asserted at the beginning of the ?rst burst of a dma transfer and will be de-asserted on the last cycle, rd_n or wr_n active pulse, of that burst. it will be reasserted shortly after the dack de-assertion, as long as the dma transfer counter was not reached. dreq will be de-asserted on the last cycle when the dma transfer counter is reached and will not be reasserted until the dma reprogramming is performed. both dreq and dack signals are programmable as active low or active high, according to the system requirements.
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 19 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller the dma start address must be initialized in the respective register, and the subsequent transfers will automatically increment the internal saf1760 memory address. a register or memory access or access to other system memory can occur in between dma bursts, whenever the bus is released because dack is de-asserted, without affecting the dma transfer counter or the current address. any memory area can be accessed by the systems dma at any starting address because there are no prede?ned memory blocks. the dma transfer must start on a word or double word address, depending on whether the data bus width is set to 16 bit or 32 bit. dma is the most ef?cient method to initialize the payload area, to reduce the cpu usage and overall system loading. the saf1760 does not implement eot to signal the end of a dma transfer. if programmed, an interrupt may be generated by the saf1760 at the end of the dma transfer. the slave dma of the saf1760 will issue a dreq to the dma controller of the system to indicate that it is programmed for transfer and data is ready. the system dma controller may also start a transfer without the need of the dreq, if the saf1760 memory is available for the data transfer and the saf1760 dma programming is completed. it is also possible that the systems dma will perform a memory-to-memory type of transfer between the system memory and the saf1760 memory. the saf1760 will be accessed in pio mode. consequently, memory read operations must be preceded by initializing the memory register (address 033ch), as described in section 7.3.1 . no irq will be generated by the saf1760 on completing the dma transfer but an internal processor interrupt may be generated to signal that the dma transfer is completed. this is mainly useful in implementing the double-buffering scheme for data transfer to optimize the usb bandwidth. the saf1760 dma programming involves: ? set the active levels of signals dreq and dack in the hw mode control register. ? the dma start address register contains the ?rst memory address at which the data transfer will start. it must be word-aligned in 16-bit data bus mode and double word aligned in 32-bit data bus mode. ? the programming of the dma con?guration register speci?es: C the type of transfer that will be performed: read or write. C the burst size, expressed in bytes, is speci?ed, regardless of the data bus width. for the same burst size, a double number of cycles will be generated in 16-bit mode data bus width as compared to 32-bit mode. C the transfer length, expressed in number of bytes, de?nes the number of bursts. the dreq will be de-asserted and asserted to generate the next burst, as long as there are bytes to be transferred. at the end of a transfer, the dreq will be de-asserted and an irq can be generated if dmaeotint (bit 3 in the interrupt register) is set. the maximum dma transfer size is equal to the maximum memory size. the transfer size can be an odd or even number of bytes, as required. if the transfer size is an odd number of bytes, the number of bytes transferred by the systems dma is equal to the next multiple of two for the 16-bit data bus width or four for the 32-bit data bus width. for a write operation, however, only the speci?ed odd number of bytes in the saf1760 memory will be affected.
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 20 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller C enable enable_dma (bit 1) of the dma con?guration register to determine the assertion of dreq immediately after setting the bit. after programming the preceding parameters, the systems dma may be enabled, waiting for the dreq to start the transfer or immediate transfer may be started. the programming of the systems dma must match the programming of the saf1760 dma parameters. only one dma transfer may take place at a time. pio mode data transfer may occur simultaneously with a dma data transfer, in the same or a different memory area. 7.4 interrupts the saf1760 will assert an irq according to the source or event in the interrupt register. the main steps to enable the irq assertion are: 1. set global_intr_en (bit 0) in the hw mode control register. 2. de?ne the irq active as level or edge in intr_level (bit 1) of the hw mode control register. 3. de?ne the irq polarity as active low or active high in intr_pol (bit 2) of the hw mode control register. these settings must match the irq settings of the host processor. by default, interrupt is level-triggered and active low. 4. program the individual interrupt enable bits in the interrupt enable register. the software will need to clear the interrupt status bits in the interrupt register before enabling individual interrupt enable bits. additional irq characteristics can be adjusted in the edge interrupt count register, as necessary, applicable only when irq is set to be edge-active; a pulse of a de?ned width is generated every time irq is active. bits 15 to 0 of the edge interrupt count register de?ne the irq pulse width. the maximum pulse width that can be programmed is ffffh, corresponding to a 1 ms pulse width. this setting is necessary for certain processors that may require a different minimum irq pulse width from the default value. the default irq pulse width set at power-on is approximately 500 ns. bits 31 to 24 of the edge interrupt count register de?ne the minimum interval between two interrupts to avoid frequent interrupts to the cpu. the default value of 00h attributed to these bits determines the normal irq generation, without any delay. when a delay is programmed and the irq becomes active after the respective delay, several irq events may have already occurred. all the interrupt events are represented by the respective bits allocated in the interrupt register. there is no mechanism to show the order or the moment of occurrence of an interrupt. the asserted bits in the interrupt register can be cleared by writing back the same value to the interrupt register. this means that writing logic 1 to each of the set bits will reset the corresponding bits to the initial inactive state.
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 21 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller the irq generation rules that apply according to the preceding settings are: ? if an event of interrupt occurs but the respective bit in the interrupt enable register is not set, then the respective interrupt register bit is set but the interrupt signal is not asserted. an interrupt will be generated when interrupt is enabled and the respective bit in the interrupt enable register is set. ? for a level trigger, an interrupt signal remains asserted until the processor clears the interrupt register by writing logic 1 to clear the interrupt register bits that are set. ? if an interrupt is made edge-sensitive and is asserted, writing to clear the interrupt register will not have any effect because the interrupt will be asserted for a prescribed amount of clock cycles. ? the clock stopping mechanism does not affect the generation of an interrupt. this is useful during suspend and resume cycles, when an interrupt is generated to signal a wake-up event. the irq generation can also be conditioned by programming the irq mask or and irq mask and registers. with the help of the irq mask and and irq mask or registers for each type of transfer (iso, int and bulk), software can determine which ptds get priority and an interrupt will be generated when the and or or conditions are met. the ptds that are set will wait until the respective bits of the remaining ptds are set and then all ptds generate an interrupt request to the cpu together. the registers de?nition shows that the and or or conditions are applicable to the same category of ptds: iso, int, atl. when an irq is generated, the ptd done map registers and the respective v bits will show which ptds were completed. the rules that apply to the irq mask and or irq mask or settings are: ? the or mask has a higher priority over the and mask. an irq is generated if bit n of the done map is set and the corresponding bit n of the or mask register is set. ? if the or mask for any done bit is not set, then the and mask comes into picture. an irq is generated if all the corresponding done bits of the and mask register are set. for example: if bits 2, 4 and 10 are set in the and mask register, an irq is generated only if bits 2, 4, 10 of the done map are set. ? if using the irq interval setting for the bulk ptd, an interrupt will only occur at the regular time interval as programmed in the atl done timeout register. even if an interrupt event occurs before the time-out of the register, no irq will be generated until the time is up. for an example on using the irq mask and or irq mask or registers without the atl done timeout register, see t ab le 5 . the and function: activate the irq only if ptds 1, 2 and 4 are done. the or function: if any of the ptds 7, 8 or 9 are done, an irq for each of the ptd will be raised.
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 22 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 7.5 phase-locked loop (pll) clock multiplier the internal pll requires a 12 mhz input, which can be a 12 mhz crystal or a 12 mhz clock already existing in the system with a precision better than 50 10 - 6 . this allows the use of a low-cost 12 mhz crystal that also minimizes electromagnetic interference (emi). when an external crystal is used, make sure the clkin pin is connected to v cc(i/o) . the pll block generates all the main internal clocks required for normal functionality of various blocks: 30 mhz, 48 mhz and 60 mhz. no external components are required for the pll operation. 7.6 power management the saf1760 implements a ?exible power management scheme, allowing various power saving stages. the usual powering scheme implies programming ehci registers and the internal hi-speed usb (usb 2.0) hub in the same way it is done in the case of a pci hi-speed usb host controller with a hi-speed usb hub attached. when the saf1760 is in suspend mode, the main internal clocks will be stopped to ensure minimum power consumption. an internal lazyclock of 100 khz 40 % will continue running. this allows initiating a resume on one of these events: ? external usb device connect or disconnect ? cs_n signal asserted when the saf1760 is accessed ? driving the suspend/wakeup_n pin to a low level the suspend/wakeup_n pin is a bidirectional pin. this pin must be connected to the gpio pins of a processor. the wake up state can be veri?ed by reading the low level of this pin. if the level is high, it means that the saf1760 is in the suspend state. the suspend/wakeup_n pin requires a pull-up because in the saf1760 suspended state the pin becomes 3-state and can be pulled down, driving it externally by switching the processors gpio line to output mode to generate the saf1760 wake-up. table 5. using the irq mask and or irq mask or registers ptd and register or register time ptd done irq 11 0 1ms1 - 21 0 - 1 - 30 0 - - - 4 1 0 3 ms 1 active because of and 50 0 - - - 60 0 - - - 7 0 1 5 ms 1 active because of or 8 0 1 6 ms 1 active because of or 9 0 1 7 ms 1 active because of or
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 23 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller the suspend/wakeup_n pin is a 3-state output. it is also an input to the internal wake-up logic. when in suspend mode, the saf1760 internal wake-up circuitry will sense the status of the suspend/wakeup_n pin: ? if it remains pulled-up, no wake-up is generated because a high is sensed by the internal wake-up circuit. ? if the pin is externally pulled low, for example, by the gpio line or just as a test by jumper, the input to the wake-up circuitry becomes low and the wake-up is internally initiated. the resume state has a clock-off count timer de?ned by bits 31 to 16 of the power-down control register. the default value of this timer is 10 ms, meaning that the resume state will be maintained for 10 ms. if during this time, the run/stop bit in the usbcmd register is set to logic 1, the host controller will go into a permanent resume; the normal functional state. if the run/stop bit is not set during the time determined by the clock-off count, the saf1760 will switch back to suspend mode after the speci?ed time. the maximum delay that can be programmed in the clock-off count ?eld is approximately 500 ms. the power-down control register allows additionally the saf1760 internal blocks to be disabled for lower power consumption as de?ned in t ab le 51 . a very low suspend current can be achieved by completely switching off the v cc(5v0) using an external pmos transistor, controlled by one of the gpio pins of the processor. when the saf1760 power is always on, the time from wake-up to suspend will be approximately 100 ms. it is necessary to wait for the clkready interrupt assertion before programming the saf1760 because internal clocks are stopped during deep-sleep suspend and restarted after the ?rst wake-up event. the occurrence of the clkready interrupt means that internal clocks are running and the normal functionality is achieved. it is estimated that the clkready interrupt will be generated less than 100 m s after the wake-up event, if the power to the saf1760 was on during suspend. if the saf1760 is used in hybrid mode and v cc(5v0) is off during suspend, a 3 ms reset pulse is required when the power is switched back on, before the resume programming sequence starts. this will ensure that internal clocks are running and all logics reach a stable initial state. 7.7 overcurrent detection the saf1760 can implement a digital or analog overcurrent detection scheme. bit 15 of the hw mode control register can be programmed to select the analog or digital overcurrent detection. an analog overcurrent detection circuit is integrated on-chip. the main features of this circuit are self reporting, automatic resetting, low-trip time and low cost. this circuit offers an easy solution at no extra hardware cost on the board. the port power will automatically be disabled by the saf1760 on an overcurrent event occurrence, by de-asserting the pswn_n signal without any software intervention.
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 24 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller when using the integrated analog overcurrent detection, the range of the overcurrent detection voltage for the saf1760 is 45 mv to 120 mv. calculation of external components should be based on the 45 mv value, with the actual overcurrent detection threshold usually positioned in the middle of the interval. for an overcurrent limit of 500 ma per port, a pmos transistor with r dson of approximately 100 m w is required. if a pmos transistor with a lower r dson is used, the analog overcurrent detection can be adjusted using a series resistor; see figure 6 . d v pmos = d v trip(oc) = d v trip(intrinsic) - (i oc(nom) r adj(oc) ), where: d v pmos = voltage drop on pmos i oc(nom) = 1 m a the digital overcurrent scheme requires using an external power switch with integrated overcurrent detection, such as lm3526, mic2526 (2 ports) or lm3544 (4 ports). these devices are controlled by pswn_n signals corresponding to each port. in the case of overcurrent occurrence, these devices will assert ocn_n signals. on ocn_n assertion, the saf1760 cuts off the port power by de-asserting pswn_n. the external integrated power switch will also automatically cut off the port power in the case of an overcurrent event, by implementing a thermal shutdown. an internal delay ?lter will prevent false overcurrent reporting because of in-rush currents when plugging a usb device. because of this internal delay, as soon as ocn_n is asserted, pswn_n will switch off the external pmos in less than 15 ms. (1) r adj(oc) is optional. fig 6. adjusting analog overcurrent detection limit (optional) 001aai637 ref5v r adj(oc) (1) 5 v saf1760 ocn_n pswn_n i oc
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 25 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 7.8 power supply figure 7 shows the saf1760 power supply connection. figure 8 shows the most commonly used power supply connection. (1) each supply voltage pin must be connected to a 100 nf decoupling capacitor (2) a 4.7 m fto10 m f electrolytic or tantalum capacitor is required on any one of the pins 5, 50 or 118. all the electrolytic or tantalum capacitors must be of low esr type (0.2 w to 2 w ). fig 7. saf1760 power supply connection (1) each supply voltage pin must be connected to a 100 nf decoupling capacitor (2) a 4.7 m fto10 m f electrolytic or tantalum capacitor is required on any one of the pins 5, 50 or 118. all the electrolytic or tantalum capacitors must be of low esr type (0.2 w to 2 w ). fig 8. most commonly used power supply connection 001aai634 6, 7 v cc(i/o) SAF1760BE 3.3 v to 5 v (1) (1) (1), (2) v cc(5v0) 10, 40, 48, 59, 67, 75, 83, 94, 104, 115 reg1v8 85 10 m f 100 nf 100 nf 100 nf 1.65 v to 3.6 v reg1v8 5, 50, 118 100 nf reg3v3 9 10 m f 100 nf 001aai635 v cc(5v0) , v cc(i/o ) SAF1760BE 6, 7, 10, 40, 48, 59, 67, 75, 83, 94, 104, 115 reg1v8 85 10 m f 100 nf 100 nf 3.3 v reg1v8 5, 50, 118 100 nf reg3v3 9 10 m f 100 nf (1) (1), (2)
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 26 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 7.8.1 hybrid mode t ab le 6 shows the description of hybrid mode. in hybrid mode (see figure 9 ), v cc(5v0) can be switched off using an external pmos transistor, controlled using one of the gpio pins of the processor. this helps to reduce the suspend current, i cc(i/o) , below 100 m a. if the saf1760 is used in hybrid mode and v cc(5v0) is off during suspend, a 3 ms reset pulse is required when power is switched back on, before the resume programming sequence starts. t ab le 7 shows the status of output pins in hybrid mode. table 6. hybrid mode voltage status v cc(5v0) off v cc(i/o) on (1) each supply voltage pin must be connected to a 100 nf decoupling capacitor (2) a 4.7 m fto10 m f electrolytic or tantalum capacitor is required on any one of the pins 5, 50 or 118. all the electrolytic or tantalum capacitors must be of low esr type (0.2 w to 2 w ). fig 9. hybrid mode table 7. pin status in hybrid mode pins v cc(i/o) v cc(5v0) status data[31:0], a[17:1], test1, test2, test3, test4, test5, test6, test7, dreq, dack, irq, suspend/wakeup_n on on normal on off high-z off x unde?ned cs_n, reset_n, rd_n, wr_n on x input off x unde?ned 001aai636 6, 7 v cc(i/o) SAF1760BE 3.3 v to 5 v v cc(5v0) 10, 40, 48, 59, 67, 75, 83, 94, 104, 115 reg1v8 85 10 m f 100 nf 100 nf 100 nf 1.65 v to 3.6 v reg1v8 5, 50, 118 100 nf reg3v3 9 10 m f 100 nf controlled by the cpu (1) (1) (1), (2)
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 27 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 7.9 power-on reset (por) figure 10 shows a possible curve of reg1v8 with dips at t2 to t3 and t4 to t5. the porp starts with a high at t0. at t1, the detector will see the passing of the trip level v trip(h) and a delay element will add another t porp before the porp drops to 0. if the dip at t4 to t5 is too short, less than 11 m s, the porp will not react and will remain low. a high on porp will be generated whenever reg1v8 drops below v trip(l) for more than 11 m s. the recommended reset input pulse length at power-on must be at least 3 ms to ensure that internal clocks are stable. the reset_n pin can be either connected to v cc(i/o) using the internal por circuit or externally controlled by the microcontroller, asic, and so on. figure 11 shows the availability of the clock with respect to the external por. (1) porp = power-on reset pulse. fig 10. internal power-on reset timing stable external clock is available at a. fig 11. clock with respect to the external power-on reset 001aak333 t0 t porp t porp t1 t2 t3 reg1v8 v trip(h) v trip(l) porp (1) t4 t5 reset_n external clock a 004aaa583
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 28 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 8. registers t ab le 8 shows the bit description of the registers. ? all registers range from 0000h to 03ffh. these registers can be read or written as double word, which is 32-bit data. in case of a 16-bit data bus width, two subsequent accesses are necessary to complete the register read or write cycle. ? operational registers range from 0000h to 01ffh. con?guration registers range from 0300h to 03ffh. table 8. register overview address register reset value references ehci capability registers 0000h caplength 20h section 8.1.1 0002h hciversion 0100h section 8.1.2 0004h hcsparams 0000 0011h section 8.1.3 0008h hccparams 0000 0086h section 8.1.4 ehci operational registers 0020h usbcmd 0008 0b00h section 8.2.1 0024h usbsts 0000 0000h section 8.2.2 0028h usbintr 0000 0000h section 8.2.3 002ch frindex 0000 0000h section 8.2.4 0060h configflag 0000 0000h section 8.2.5 0064h portsc1 0000 2000h section 8.2.6 0130h iso ptd done map 0000 0000h section 8.2.7 0134h iso ptd skip map ffff ffffh section 8.2.8 0138h iso ptd last ptd 0000 0000h section 8.2.9 0140h int ptd done map 0000 0000h section 8.2.10 0144h int ptd skip map ffff ffffh section 8.2.11 0148h int ptd last ptd 0000 0000h section 8.2.12 0150h atl ptd done map 0000 0000h section 8.2.13 0154h atl ptd skip map ffff ffffh section 8.2.14 0158h atl ptd last ptd 0000 0000h section 8.2.15 0200h to 02ffh reserved - - con?guration registers 0300h hw mode control 0000 0100h section 8.3.1 0304h chip id 0001 1761h section 8.3.2 0308h scratch 0000 0000h section 8.3.3 030ch sw reset 0000 0000h section 8.3.4 0330h dma con?guration 0000 0000h section 8.3.5 0334h buffer status 0000 0000h section 8.3.6 0338h atl done timeout 0000 0000h section 8.3.7 033ch memory 0000 0000h section 8.3.8 0340h edge interrupt count 0000 000fh section 8.3.9
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 29 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 8.1 ehci capability registers 8.1.1 caplength register the bit description of the capability length (caplength) register is given in t ab le 9 . 8.1.2 hciversion register t ab le 10 shows the bit description of the host controller interface version number (hciversion) register. 0344h dma start address 0000 0000h section 8.3.10 0354h power-down control 03e8 1ba0h section 8.3.11 0374h port 1 control 0086 0086h section 8.3.12 interrupt registers 0310h interrupt 0000 0000h section 8.4.1 0314h interrupt enable 0000 0000h section 8.4.2 0318h iso irq mask or 0000 0000h section 8.4.3 031ch int irq mask or 0000 0000h section 8.4.4 0320h atl irq mask or 0000 0000h section 8.4.5 0324h iso irq mask and 0000 0000h section 8.4.6 0328h int irq mask and 0000 0000h section 8.4.7 032ch atl irq mask and 0000 0000h section 8.4.8 table 8. register overview continued address register reset value references table 9. caplength - capability length register (address 0000h) bit description bit symbol access value description 7 to 0 caplength[7:0] r 20h capability length : this is used as an offset. it is added to the register base to ?nd the beginning of the operational register space. table 10. hciversion - host controller interface version number register (address 0002h) bit description bit symbol access value description 15 to 0 hciversion[15:0] r 0100h host controller interface version number : it contains a bcd encoding of the version number of the interface to which the host controller interface conforms.
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 30 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 8.1.3 hcsparams register the host controller structural parameters (hcsparams) register is a set of ?elds that are structural parameters. the bit allocation is given in t ab le 11 . [1] for details on register bit description, refer to ref . 2 enhanced host controller interf ace speci? cation f or univ ersal ser ial bus re v . 1.0 . table 11. hcsparams - host controller structural parameters register (address 0004h) bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset 00000000 access rrrrrrrr bit 23 22 21 20 19 18 17 16 symbol dpn[3:0] reserved p_indicat or reset 00000000 access rrrrrrrr bit 15 14 13 12 11 10 9 8 symbol n_cc[3:0] n_pcc[3:0] reset 00000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol prr reserved ppc n_ports[3:0] reset 00010001 access rrrrrrrr table 12. hcsparams - host controller structural parameters register (address 0004h) bit description bit symbol description [1] 31 to 24 - reserved; write logic 0 23 to 20 dpn[3:0] debug port number : this ?eld identi?es which of the host controller ports is the debug port. 19 to 17 - reserved; write logic 0 16 p_indicator port indicators : this bit indicates whether the ports support port indicator control. 15 to 12 n_cc[3:0] number of companion controller : this ?eld indicates the number of companion controllers associated with this hi-speed usb host controller. 11 to 8 n_pcc[3:0] number of ports per companion controller : this ?eld indicates the number of ports supported per companion host controller. 7 prr port routing rules : this ?eld indicates the method used to map ports to companion controllers. 6 to 5 - reserved; write logic 0 4 ppc port power control : this ?eld indicates whether the host controller implementation includes port power control. 3 to 0 n_ports[3:0] n_ports : this ?eld speci?es the number of physical downstream ports implemented on this host controller.
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 31 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 8.1.4 hccparams register the host controller capability parameters (hccparams) register is a four byte register, and the bit allocation is given in t ab le 13 . [1] for details on register bit description, refer to ref . 2 enhanced host controller interf ace speci? cation f or univ ersal ser ial bus re v . 1.0 . table 13. hccparams - host controller capability parameters register (address 0008h) bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset 00000000 access rrrrrrrr bit 23 22 21 20 19 18 17 16 symbol reserved reset 00000000 access rrrrrrrr bit 15 14 13 12 11 10 9 8 symbol eecp[7:0] reset 00000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol ist[3:0] reserved aspc pflf reserved reset 10000110 access rrrrrrrr table 14. hccparams - host controller capability parameters register (address 0008h) bit description bit symbol description [1] 31 to 16 - reserved; write logic 0 15 to 8 eecp[7:0] ehci extended capabilities pointer : default = implementation dependent. this optional ?eld indicates the existence of a capabilities list. 7 to 4 ist[3:0] isochronous scheduling threshold : default = implementation dependent. this ?eld indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule. 3 - reserved; write logic 0 2 aspc asynchronous schedule park capability : default = implementation dependent. if this bit is set to logic 1, the host controller supports the park feature for high-speed transfer descriptors in the asynchronous schedule. 1 pflf programmable frame list flag : default = implementation dependent. if this bit is cleared, the system software must use a frame list length of 1024 elements with this host controller. if pflf is set, the system software can specify and use a smaller frame list and con?gure the host through the frame list size (fls) ?eld of the usbcmd register. 0 - reserved; write logic 0
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 32 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 8.2 ehci operational registers 8.2.1 usbcmd register the usb command (usbcmd) register indicates the command to be executed by the serial host controller. writing to this register causes a command to be executed. t ab le 15 shows the usbcmd register bit allocation. [1] the reserved bits should always be written with the reset value. [1] for details on register bit description, refer to ref . 2 enhanced host controller interf ace speci? cation f or univ ersal ser ial bus re v . 1.0 . table 15. usbcmd - usb command register (address 0020h) bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved [1] reset 00001000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved [1] reset 00001011 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol lhcr reserved [1] hcreset rs reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 16. usbcmd - usb command register (address 0020h) bit description bit symbol description [1] 31 to 8 - reserved 7 lhcr light host controller reset (optional): if implemented, it allows the driver software to reset the ehci controller without affecting the state of the ports or the relationship to the companion host controllers. if not implemented, a read of this ?eld will always return logic 0. 6 to 2 - reserved 1 hcreset host controller reset : this control bit is used by the software to reset the host controller. 0rs run/stop : 1 = run. the host controller executes the schedule. 0 = stop.
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 33 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 8.2.2 usbsts register the usb status (usbsts) register indicates pending interrupts and various states of the host controller. the status resulting from a transaction on the serial bus is not indicated in this register. software clears register bits by writing ones to them. the bit allocation is given in t ab le 17 . [1] the reserved bits should always be written with the reset value. [1] for details on register bit description, refer to ref . 2 enhanced host controller interf ace speci? cation f or univ ersal ser ial bus re v . 1.0 . table 17. usbsts - usb status register (address 0024h) bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved [1] flr pcd reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 18. usbsts - usb status register (address 0024h) bit description bit symbol description [1] 31 to 4 - reserved; write logic 0 3 flr frame list rollover : the host controller sets this bit to logic 1 when the frame list index rolls over from its maximum value to zero. 2 pcd port change detect : the host controller sets this bit to logic 1 when any port, where the po bit is cleared, has a change to a one or a fpr bit changes to a one as a result of a j-k transition detected on a suspended port. 1 to 0 - reserved
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 34 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 8.2.3 usbintr register the usb interrupt (usbintr) register is a read or write register located at 0028h. all the bits in this register are reserved. 8.2.4 frindex register the frame index (frindex) register is used by the host controller to index into the periodic frame list. the register updates every 125 m s (once each microframe). bits n to 3 are used to select a particular entry in the periodic frame list during periodic schedule execution. the number of bits used for the index depends on the size of the frame list as set by the system software in the frame list size (fls) ?eld of the usbcmd register. this register must be written as a double word. a word-only write (16-bit mode) produces unde?ned results. a write to this register while the run/stop (r/s) bit is set produces unde?ned results. writes to this register also affect the sof value. the bit allocation is given in t ab le 19 . [1] the reserved bits should always be written with the reset value. [1] for details on register bit description, refer to ref . 2 enhanced host controller interf ace speci? cation f or univ ersal ser ial bus re v . 1.0 . table 19. frindex - frame index register (address: 002ch) bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved [1] frindex[13:8] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol frindex[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 20. frindex - frame index register (address: 002ch) bit description bit symbol description [1] 31 to 14 - reserved 13 to 0 frindex[13:0] frame index : bits in this register are used for the frame number in the sof packet and as the index into the frame list. the value in this register increments at the end of each time frame. for example, microframe.
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 35 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 8.2.5 configflag register the bit allocation of the con?gure flag (configflag) register is given in t ab le 21 . [1] the reserved bits should always be written with the reset value. [1] for details on register bit description, refer to ref . 2 enhanced host controller interf ace speci? cation f or univ ersal ser ial bus re v . 1.0 . 8.2.6 portsc1 register the port status and control (portsc) register (bit allocation: t ab le 23 ) is in the power well. it is reset by hardware only when the auxiliary power is initially applied or in response to a host controller reset. the initial conditions of a port are: ? no peripheral connected ? port disabled if the port has power control, software cannot change the state of the port until it sets port power bits. software must not attempt to change the state of the port until the power is stable on the port (maximum delay is 20 ms from the transition). table 21. configflag - con?gure flag register (address 0060h) bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved [1] cf reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 22. configflag - con?gure flag register (address 0060h) bit description bit symbol description [1] 31 to 1 - reserved 0cf con?gure flag : the host software sets this bit as the last action when it is con?guring the host controller. this bit controls the default port-routing control logic.
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 36 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller [1] the reserved bits should always be written with the reset value. table 23. portsc1 - port status and control 1 register (address 0064h) bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved [1] ptc[3:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol pic[1:0] po pp ls[1:0] reserved [1] pr reset 00100000 access r r r/w r/w r/w r/w r/w r bit 7 6 5 4 3 2 1 0 symbol susp fpr reserved [1] ped ecsc eccs reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r table 24. portsc1 - port status and control 1 register (address 0064h) bit description bit symbol description [1] 31 to 20 - reserved 19 to 16 ptc[3:0] port test control : when this ?eld is zero, the port is not operating in test mode. a nonzero value indicates that it is operating in test mode indicated by the value. 15 to 14 pic[1:0] port indicator control : writing to this ?eld has no effect if the p_indicator bit in the hcsparams register is logic 0. for a description on how these bits are implemented, refer to ref . 1 univ ersal ser ial bus speci? cation re v . 2.0 . [2] 13 po port owner : this bit unconditionally goes to logic 0 when the con?gured bit in the configflag register makes a logic 0 to logic 1 transition. this bit unconditionally goes to logic 1 whenever the con?gured bit is logic 0. 12 pp port power : the function of this bit depends on the value of the port power control (ppc) ?eld in the hcsparams register. 11 to 10 ls[1:0] line status : this ?eld re?ects the current logical levels of the dp (bit 11) and dm (bit 10) signal lines. 9 - reserved 8pr port reset : logic 1 means the port is in the reset state. logic 0 means the port is not in reset. [2] 7 susp suspend : logic 1 means the port is in the suspend state. logic 0 means the port is not suspended. [2] 6 fpr force port resume : logic 1 means resume detected or driven on the port. logic 0 means no resume (k-state) detected or driven on the port. [2] 5 to 3 - reserved
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 37 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller [1] for details on register bit description, refer to ref . 2 enhanced host controller interf ace speci? cation f or univ ersal ser ial bus re v . 1.0 . [2] these ?elds read logic 0, if the pp (port power) bit in register portsc1 is logic 0. 8.2.7 iso ptd done map register the bit description of the register is given in t ab le 25 . this register represents a direct map of the done status of the 32 ptds. the bit corresponding to a certain ptd will be set to logic 1 as soon as that ptd execution is completed. reading the done map register will clear all the bits that are set to logic 1, and the next reading will re?ect the updated status of new executed ptds. 8.2.8 iso ptd skip map register t ab le 26 shows the bit description of the register. when a bit in the ptd skip map is set to logic 1, the corresponding ptd will be skipped, independent of the v bit setting. the information in that ptd is not processed. for example, nextptdpointer will not affect the order of processing of ptds. the skip bit should not normally be set on the position indicated by nextptdpointer. 8.2.9 iso ptd last ptd register t ab le 27 shows the bit description of the iso ptd last ptd register. once the lastptd bit corresponding to a ptd is set, this will be the last ptd processed (checking v = logic 1) in that ptd category. subsequently, the process will restart with the ?rst ptd of that group. this is useful to reduce the time in which all the ptds, the 2 ped port enabled/disabled : logic 1 means enable. logic 0 means disable. [2] 1 ecsc connect status change : logic 1 means change in eccs. logic 0 means no change. [2] 0 eccs current connect status : logic 1 indicates a device is present on the port. logic 0 indicates no device is present. [2] table 24. portsc1 - port status and control 1 register (address 0064h) bit description continued bit symbol description [1] table 25. iso ptd done map register (address 0130h) bit description bit symbol access value description 31 to 0 iso_ptd_done _map[31:0] r 0000 0000h iso ptd done map : done map for each of the 32 ptds for the iso transfer table 26. iso ptd skip map register (address 0134h) bit description bit symbol access value description 31 to 0 iso_ptd_skip _map[31:0] r/w ffff ffffh iso ptd skip map : skip map for each of the 32 ptds for the iso transfer. table 27. iso ptd last ptd register (address 0138h) bit description bit symbol access value description 31 to 0 iso_ptd_last _ptd[31:0] r/w 0000 0000h iso ptd last ptd : last ptd of the 32 ptds is indicated by the 32 bitmap. 1h one ptd in iso 2h two ptds in iso 4h three ptds in iso
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 38 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller respective memory space, would be checked, especially if only a few ptds are de?ned. the lastptd bit must be normally set to a higher position than any other position indicated by the nextptdpointer from an active ptd. 8.2.10 int ptd done map register the bit description of the register is given in t ab le 28 . this register represents a direct map of the done status of the 32 ptds. the bit corresponding to a certain ptd will be set to logic 1 as soon as that ptd execution is completed. reading the done map register will clear all the bits that are set to logic 1, and the next reading will re?ect the updated status of new executed ptds. 8.2.11 int ptd skip map register t ab le 29 shows the bit description of the int ptd skip map register. when a bit in the ptd skip map is set to logic 1, the corresponding ptd will be skipped, independent of the v bit setting. the information in that ptd is not processed. for example, nextptdpointer will not affect the order of processing of ptds. the skip bit must not be normally set on the position indicated by nextptdpointer. 8.2.12 int ptd last ptd register the bit description of the register is given in t ab le 30 . once the lastptd bit corresponding to a ptd is set, this will be the last ptd processed (checking v = logic 1) in that ptd category. subsequently, the process will restart with the ?rst ptd of that group. this is useful to reduce the time in which all the ptds, the respective memory space, would be checked, especially if only a few ptds are de?ned. the lastptd bit must be normally set to a higher position than any other position indicated by the nextptdpointer from an active ptd. table 28. int ptd done map register (address 0140h) bit description bit symbol access value description 31 to 0 int_ptd_done_ map[31:0] r 0000 0000h int ptd done map : done map for each of the 32 ptds for the int transfer table 29. int ptd skip map register (address 0144h) bit description bit symbol access value description 31 to 0 int_ptd_skip _map[31:0] r/w ffff ffffh int ptd skip map : skip map for each of the 32 ptds for the int transfer table 30. int ptd last ptd register (address 0148h) bit description bit symbol access value description 31 to 0 int_ptd_last _ptd[31:0] r/w 0000 0000h int ptd last ptd : last ptd of the 32 ptds. 1h one ptd in int 2h two ptds in int 3h three ptds in int
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 39 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 8.2.13 atl ptd done map register t ab le 31 shows the bit description of the atl ptd done map register. this register represents a direct map of the done status of the 32 ptds. the bit corresponding to a certain ptd will be set to logic 1 as soon as that ptd execution is completed. reading the done map register will clear all the bits that are set to logic 1, and the next reading will re?ect the updated status of new executed ptds. 8.2.14 atl ptd skip map register the bit description of the register is given in t ab le 32 . when a bit in the ptd skip map is set to logic 1, the corresponding ptd will be skipped, independent of the v bit setting. the information in that ptd is not processed. for example, nextptdpointer will not affect the order of processing of ptds. the skip bit must not normally be set on the position indicated by nextptdpointer. 8.2.15 atl ptd last ptd register the bit description of the atl ptd last ptd register is given in t ab le 33 . once the lastptd bit corresponding to a ptd is set, this will be the last ptd processed (checking v = logic 1) in that ptd category. subsequently, the process will restart with the ?rst ptd of that group. this is useful to reduce the time in which all the ptds, the respective memory space, would be checked, especially if only a few ptds are de?ned. the lastptd bit must normally be set to a higher position than any other position indicated by the nextptdpointer from an active ptd. table 31. atl ptd done map register (address 0150h) bit description bit symbol access value description 31 to 0 atl_ptd_done_ map[31:0] r 0000 0000h atl ptd done map : done map for each of the 32 ptds for the atl transfer table 32. atl ptd skip map register (address 0154h) bit description bit symbol access value description 31 to 0 atl_ptd_skip_ map[31:0] r/w ffff ffffh atl ptd skip map : skip map for each of the 32 ptds for the atl transfer table 33. atl ptd last ptd register (address 0158h) bit description bit symbol access value description 31 to 0 atl_ptd_last _ptd[31:0] r/w 0000 0000h atl ptd last ptd : last ptd of the 32 ptds as indicated by the 32 bitmap. 1h one ptd in atl 2h two ptds in atl 4h three ptds in atl
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 40 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 8.3 con?guration registers 8.3.1 hw mode control register t ab le 34 shows the bit allocation of the register. [1] the reserved bits should always be written with the reset value. table 34. hw mode control - hardware mode control register (address 0300h) bit allocation bit 31 30 29 28 27 26 25 24 symbol all_atx_ reset reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol ana_digi_ oc reserved [1] data_bus _width reset 00000001 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved dack_ pol dreq_ pol reserved [1] intr_pol intr_ level global_ intr_en reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 35. hw mode control - hardware mode control register (address 0300h) bit description bit symbol description 31 all_atx_reset all atx reset : for debugging purposes (not used normally). 1 enable reset, then write back logic 0 0 no reset 30 to 16 - reserved; write logic 0 15 ana_digi_oc analog digital overcurrent : this bit selects analog or digital overcurrent detection on pins oc1_n, oc2_n and oc3_n. 0 digital overcurrent 1 analog overcurrent 14 to 9 - reserved; write logic 0 8 data_bus_width data bus width : 0 de?nes a 16-bit data bus width 1 sets a 32-bit data bus width 7 - reserved; write logic 0 6 dack_pol dack polarity : 1 indicates that the dack input is active high 0 indicates active low
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 41 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 8.3.2 chip id register read this register to get the id of the saf1760. the upper word of the register contains the hardware version number and the lower word contains the chip id. t ab le 36 shows the bit description of the register. 8.3.3 scratch register this register is for testing and debugging purposes only. the value read back must be the same as the value that was written. the bit description of this register is given in t ab le 37 . 5 dreq_pol dreq polarity : 1 indicates that the dreq output is active high 0 indicates active low 4 to 3 - reserved; write logic 0 2 intr_pol interrupt polarity : 0 active low 1 active high 1 intr_level interrupt level : 0 int is level triggered. 1 int is edge triggered. a pulse of certain width is generated. 0 global_intr_en global interrupt enable : this bit must be set to logic 1 to enable the irq signal assertion. 0 irq assertion is disabled. irq will never be asserted, regardless of other settings or irq events. 1 irq assertion is enabled. irq will be asserted according to the interrupt enable register, and events setting and occurrence. table 35. hw mode control - hardware mode control register (address 0300h) bit description continued bit symbol description table 36. chip id - chip identi?er register (address 0304h) bit description bit symbol access value description 31 to 0 chipid[31:0] r 0001 1761h chip id : this register represents the hardware version number (0001h) and the chip id (1761h). remark: the chip id is for internal use to identify the saf176x product family. table 37. scratch register (address 0308h) bit description bit symbol access value description 31 to 0 scratch[31:0] r/w 0000 0000h scratch : for testing and debugging purposes
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 42 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 8.3.4 sw reset register t ab le 38 shows the bit allocation of the register. [1] the reserved bits should always be written with the reset value. table 38. sw reset - software reset register (address 030ch) bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved [1] reset_ hc reset_ all reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 39. sw reset - software reset register (address 030ch) bit description bit symbol description 31 to 2 - reserved; write logic 0 1 reset_hc reset host controller : reset only the host controller-speci?c registers (only registers with address below 300h). 0 no reset 1 enable reset 0 reset_all reset all : reset all the host controller and cpu interface registers. 0 no reset 1 enable reset
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 43 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 8.3.5 dma con?guration register the bit allocation of the dma con?guration register is given in t ab le 40 . [1] the reserved bits should always be written with the reset value. table 40. dma con?guration register (address 0330h) bit allocation bit 31 30 29 28 27 26 25 24 symbol dma_counter[23:16] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol dma_counter[15:8] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol dma_counter[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved [1] burst_len[1:0] enable_ dma dma_read _write_ sel reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 41. dma con?guration register (address 0330h) bit description bit symbol description 31 to 8 dma_counter[23:0] dma counter : the number of bytes to be transferred (read or write). remark: different number of bursts will be generated for the same transfer length programmed in 16-bit and 32-bit modes because dma_counter is in number of bytes. 7 to 4 - reserved 3 to 2 burst_len[1:0] dma burst length : 00 single dma burst 01 4-cycle dma burst 10 8-cycle dma burst 11 16-cycle dma burst 1 enable_dma enable dma : 0 terminate dma 1 enable dma 0 dma_read_write_sel dma read/write select : indicates if the dma operation is a write or read to or from the saf1760. 0 dma write to the saf1760 internal ram is set 1 dma read from the saf1760 internal ram
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 44 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 8.3.6 buffer status register the buffer status register is used to indicate the hc that a particular ptd buffer (that is, atl, int and iso) contains at least one ptd that must be scheduled. once software sets the buffer filled bit of a particular transfer in the buffer status register, the hc will start traversing through ptd headers that are not marked for skipping and are valid ptds. remark: software can set these bits during the initialization. t ab le 42 shows the bit allocation of the buffer status register. [1] the reserved bits should always be written with the reset value. table 42. buffer status register (address 0334h) bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved [1] iso_buf_ fill int_buf_ fill atl_buf_ fill reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 43. buffer status register (address 0334h) bit description bit symbol description 31 to 3 - reserved 2 iso_buf_fill iso buffer filled : 1 indicates one of the iso ptds is ?lled, and the iso ptd area will be processed. 0 indicates there is no ptd in this area. therefore, processing of the iso ptds will completely be skipped. 1 int_buf_fill int buffer filled : 1 indicates one of the int ptds is ?lled, and the int ptd area will be processed. 0 indicates there is no ptd in this area. therefore, processing of the int ptds will completely be skipped. 0 atl_buf_fill atl buffer filled : 1 indicates one of the atl ptds is ?lled, and the atl ptd area will be processed. 0 indicates there is no ptd in this area. therefore, processing of the atl ptds will completely be skipped.
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 45 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 8.3.7 atl done timeout register the bit description of the atl done timeout register is given in t ab le 44 . 8.3.8 memory register the memory register contains the base memory read address and the respective bank. this register needs to be set only before a ?rst memory read cycle. once written, the address will be latched for the bank and will be incremented for every read of that bank, until a new address for that bank is written to change the address pointer. the bit description of the register is given in t ab le 45 . [1] the reserved bits should always be written with the reset value. table 44. atl done timeout register (address 0338h) bit description bit symbol access value description 31 to 0 atl_done_ timeout[31:0] r/w 0000 0000h atl done timeout : this register determines the atl done time-out interrupt. this register de?nes the time-out in milliseconds after which the saf1760 asserts the int line, if enabled. it is applicable to atl done ptds only. table 45. memory register (address 033ch) bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved [1] mem_bank_sel[1:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol start_addr_mem_read[15:8] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol start_addr_mem_read[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 46. memory register (address 033ch) bit description bit symbol description 31 to 18 - reserved 17 to 16 mem_bank_ sel[1:0] memory bank select : up to four memory banks can be selected. for details on internal memory read description, see section 7.3.1 . applicable to pio mode memory read or write data transfers only. 15 to 0 start_addr_ mem_ read[15:0] start address for memory read cycles : the start address for a series of memory read cycles at incremental addresses in a contiguous space. applicable to pio mode memory read data transfers only.
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 46 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 8.3.9 edge interrupt count register t ab le 47 shows the bit allocation of the register. [1] the reserved bits should always be written with the reset value. table 47. edge interrupt count register (address 0340h) bit allocation bit 31 30 29 28 27 26 25 24 symbol min_width[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol no_of_clk[15:8] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol no_of_clk[7:0] reset 00001111 access r/w r/w r/w r/w r/w r/w r/w r/w table 48. edge interrupt count register (address 0340h) bit description bit symbol description 31 to 24 min_width [7:0] minimum width : indicates the minimum width between two edge interrupts in m sofs (1 m sof = 125 m s). this is not valid for level interrupts. a count of zero means that interrupts occur as and when an event occurs. 23 to 16 - reserved 15 to 0 no_of_clk [15:0] number of clocks : count in number of clocks that the edge interrupt must be kept asserted on the interface. the default value is 000fh. thus, 15 cycles of 30 mhz clock will make the default irq pulse width approximately 500 ns.
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 47 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 8.3.10 dma start address register this register de?nes the start address select for the dma read and write operations. see t ab le 49 for the bit allocation. [1] the reserved bits should always be written with the reset value. table 49. dma start address register (address 0344h) bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved [1] reset 00000000 access wwwwwwww bit 23 22 21 20 19 18 17 16 symbol reserved [1] reset 00000000 access wwwwwwww bit 15 14 13 12 11 10 9 8 symbol start_addr_dma[15:8] reset 00000000 access wwwwwwww bit 7 6 5 4 3 2 1 0 symbol start_addr_dma[7:0] reset 00000000 access wwwwwwww table 50. dma start address register (address 0344h) bit description bit symbol description 31 to 16 - reserved 15 to 0 start_addr_ dma[15:0] start address for dma : the start address for dma read or write cycles.
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 48 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 8.3.11 power-down control register this register is used to turn off power to the internal blocks of the saf1760 to obtain maximum power savings. t ab le 51 shows the bit allocation of the register. [1] the reserved bits should always be written with the reset value. table 51. power-down control register (address 0354h) bit allocation bit 31 30 29 28 27 26 25 24 symbol clk_off_counter[15:8] reset 00000011 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol clk_off_counter[7:0] reset 11101000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved [1] port3_ pd port2_ pd vbatdet_ pwr reserved [1] reset 000110 1 1 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved [1] biasen vreg_on oc3_pwr oc2_pwr oc1_pwr hc_clk_en reset 1010000 0 access r/w r/w r/w r/w r/w r/w r/w r/w table 52. power-down control register (address 0354h) bit description bit [1] symbol description 31 to 16 clk_off_ counter [15:0] clock off counter : determines the wake-up status duration after any wake-up event before the saf1760 goes back into suspend mode. this time-out is applicable only if, during the given interval, the host controller is not programmed back to the normal functionality. 03e8h the default value. it determines the default wake-up interval of 10 ms. a value of zero implies that the host controller never wakes up on any of the events. this may be useful when using the saf1760 as a peripheral to save power by permanently programming the host controller in suspend. ffffh the maximum value. it determines a maximum wake-up time of 500 ms. the setting of this register is based on the 100 khz 40 % lazyclock frequency. it is a multiple of 10 m s period. remark: in 16-bit mode, the default value is 17e8h. a write operation to these bits with any value ?xes the clock off counter at 1400h. this value is equivalent to a ?xed wake-up time of 50 ms. 15 to 13 - reserved 12 port3_pd port 3 pull-down : controls port 3 pull-down resistors. 0 port 3 internal pull-down resistors are not connected. 1 port 3 internal pull-down resistors are connected. 11 port2_pd port 2 pull-down : controls port 2 pull-down resistors. 0 port 2 internal pull-down resistors are not connected. 1 port 2 internal pull-down resistors are connected.
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 49 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller [1] for a 32-bit operation, the default wake-up counter value is 10 m s. for a 16-bit operation, the wake-up counter value is 50 ms. in the 16-bit operation, read and write back the same value on initialization. 10 vbatdet_pw r v bat detector powered : controls the power to the v bat detector. 0 v bat detector is powered or enabled in suspend. 1 v bat detector is not powered or disabled in suspend. 9 to 6 - reserved; write reset value 5 biasen bias circuits powered : controls the power to internal bias circuits. 0 internal bias circuits are not powered in suspend. 1 internal bias circuits are powered in suspend. 4 vreg_on v reg powered : enables or disables the internal 3.3 v and 1.8 v regulators when the saf1760 is in suspend. 0 internal regulators are normally powered in suspend. 1 internal regulators switch to low power mode (in suspend mode). 3 oc3_pwr oc3_n powered : controls the powering of the overcurrent detection circuitry for port 3. 0 overcurrent detection is powered-on or enabled during suspend. 1 overcurrent detection is powered-off or disabled during suspend. this may be useful when connecting a faulty device while the system is in standby. 2 oc2_pwr oc2_n powered : controls the powering of the overcurrent detection circuitry for port 2. 0 overcurrent detection is powered-on or enabled during suspend. 1 overcurrent detection is powered-off or disabled during suspend. this may be useful when connecting a faulty device while the system is in standby. 1 oc1_pwr oc1_n powered : controls the powering of the overcurrent detection circuitry for port 1. 0 overcurrent detection is powered-on or enabled during suspend. 1 overcurrent detection is powered-off or disabled during suspend. this may be useful when connecting a faulty device while the system is in standby. 0 hc_clk_en host controller clock enabled : controls internal clocks during suspend. 0 clocks are disabled during suspend. this is the default value. only the lazyclock of 100 khz 40 % will be left running in suspend if this bit is logic 0. if clocks are stopped during suspend, clkready irq will be generated when all clocks are running stable. 1 all clocks are enabled even in suspend. table 52. power-down control register (address 0354h) bit description continued bit [1] symbol description
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 50 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 8.3.12 port 1 control register the values read from the lower 16 bits and the upper 16 bits of this register are always the same. t ab le 53 shows the bit allocation of the register. [1] for correct port 1 initialization, write 0080 0018h to this register after power-on. table 53. port 1 control register (address 0374h) bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol port1_ init2 reserved reset 10000110 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol port1_ init1 reserved port1_power[1:0] reserved reset 00010110 access r/w r/w r/w r/w r/w r/w r/w r/w table 54. port 1 control register (address 0374h) bit description bit [1] symbol description 31 to 24 - reserved; write reset value 23 port1_init2 port 1 initialization 2 : write logic 1 at the saf1760 initialization. it will clear both this bit and bit 7. affects only port 1. 22 to 8 - reserved 7 port1_init1 port 1 initialization 1 : must be reset to logic 0 at power-up initialization for correct operation of port 1. correct host controller functionality is not ensured if set to logic 1 (affects only port 1). to clear this bit, logic 1 must be written to bit 23 during the saf1760 initialization. this is not required for the normal functionality of port 2 and port 3. 6 to 5 - reserved 4 to 3 port1_power[1:0] port 1 power : set these bits to 11b. these bits must be set to enable port 1 power. 2 to 0 - reserved; write reset value
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 51 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 8.4 interrupt registers 8.4.1 interrupt register the bits of this register indicate the interrupt source, de?ning the events that determined the int generation. clearing the bits that were set because of the events listed is done by writing back logic 1 to the respective position. all bits must be reset before enabling new interrupt events. these bits will be set, regardless of the setting of bit global_intr_en in the hw mode control register. t ab le 55 shows the bit allocation of the interrupt register. [1] the reserved bits should always be written with the reset value. table 55. interrupt register (address 0310h) bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved [1] iso_irq atl_irq reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol int_irq clk ready hc_susp reserved [1] dmaeot int reserved [1] sofitlint reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 52 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller table 56. interrupt register (address 0310h) bit description bit symbol description 31 to 10 - reserved; write reset value 9 iso_irq iso irq : indicates that an iso ptd was completed, or the ptds corresponding to the bits set in the iso irq mask and or iso irq mask or register bits combination were completed. the irq line will be asserted if the respective enable bit in the hcinterruptenable register is set. 0 no iso ptd event occurred. 1 iso ptd event occurred. for details, see section 7.4 . 8 atl_irq atl irq : indicates that an atl ptd was completed, or the ptds corresponding to the bits set in the atl irq mask and or atl irq mask or register bits combination were completed. the irq line will be asserted if the respective enable bit in the hcinterruptenable register is set. 0 no atl ptd event occurred. 1 atl ptd event occurred. for details, see section 7.4 . 7 int_irq int irq : indicates that an int ptd was completed, or the ptds corresponding to the bits set in the int irq mask and or int irq mask or register bits combination were completed. the irq line will be asserted if the respective enable bit in the hcinterruptenable register is set. 0 no int ptd event occurred. 1 int ptd event occurred. for details, see section 7.4 . 6 clkready clock ready : indicates that internal clock signals are running stable. the irq line will be asserted if the respective enable bit in the hcinterruptenable register is set. 0 no clkready event has occurred. 1 clkready event occurred. 5 hc_susp host controller suspend : indicates that the host controller has entered suspend mode. the irq line will be asserted if the respective enable bit in the hcinterruptenable register is set. 0 the host controller did not enter suspend mode. 1 the host controller entered suspend mode. if the interrupt service routine (isr) accesses the saf1760, it will wake up for the time speci?ed in bits 31 to 16 of the power-down control register. 4 - reserved; write reset value 3 dmaeot int dma eot interrupt : indicates the dma transfer completion. the irq line will be asserted if the respective enable bit in the hcinterruptenable register is set. 0 no dma transfer is completed. 1 dma transfer is complete. 2 - reserved; write reset value; value is zero just after reset and changes to one after a short while 1 sofitlint sot itl interrupt : the irq line will be asserted if the respective enable bit in the hcinterruptenable register is set. 0 no sof event has occurred. 1 an sof event has occurred. 0 - reserved; write reset value; value is zero just after reset and changes to one after a short while
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 53 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 8.4.2 interrupt enable register this register allows enabling or disabling of the irq generation because of various events as described in t ab le 57 . [1] the reserved bits should always be written with the reset value. table 57. interrupt enable register (address 0314h) bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved [1] iso_irq_e atl_irq _e reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol int_irq_e clkready _e hcsusp_e reserved [1] dmaeot int_e reserved [1] sofitlint _e reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 58. interrupt enable register (address 0314h) bit description bit symbol description 31 to 10 - reserved; write logic 0 9 iso_irq_e iso irq enable : controls the irq assertion when one or more iso ptds matching the iso irq mask and or iso irq mask or register bits combination are completed. 0 no irq will be asserted when iso ptds are completed. 1 irq will be asserted. for details, see section 7.4 . 8 atl_irq_e atl irq enable : controls the irq assertion when one or more atl ptds matching the atl irq mask and or atl irq mask or register bits combination are completed. 0 no irq will be asserted when atl ptds are completed. 1 irq will be asserted. for details, see section 7.4 . 7 int_irq_e int irq enable : controls the irq assertion when one or more int ptds matching the int irq mask and or int irq mask or register bits combination are completed. 0 no irq will be asserted when int ptds are completed. 1 irq will be asserted. for details, see section 7.4 .
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 54 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 8.4.3 iso irq mask or register each bit of this register corresponds to one of the 32 iso ptds de?ned, and is a hardware irq mask for each ptd done map. see t ab le 59 for bit description. for details, see section 7.4 . 8.4.4 int irq mask or register each bit of this register (see t ab le 60 ) corresponds to one of the 32 int ptds de?ned, and is a hardware irq mask for each ptd done map. for details, see section 7.4 . 8.4.5 atl irq mask or register each bit of this register corresponds to one of the 32 atl ptds de?ned, and is a hardware irq mask for each ptd done map. see t ab le 61 for bit description. for details, see section 7.4 . 6 clkready_e clock ready enable : enables the irq assertion when internal clock signals are running stable. useful after wake-up. 0 no irq will be generated after a clkready_e event. 1 irq will be generated after a clkready_e event. 5 hcsusp_e host controller suspend enable : enables the irq generation when the host controller enters suspend mode. 0 no irq will be generated when the host controller enters suspend mode. 1 irq will be generated when the host controller enters suspend mode. 4 - reserved; write logic 0 3 dmaeotint_e dma eot interrupt enable : controls assertion of irq on the dma transfer completion. 0 no irq will be generated when a dma transfer is completed. 1 irq will be asserted when a dma transfer is completed. 2 - reserved; must be written with logic 0 1 sofitlint_e sot itl interrupt enable : controls the irq generation at every sof occurrence. 0 no irq will be generated on an sof occurrence. 1 irq will be asserted at every sof. 0 - reserved; must be written with logic 0 table 58. interrupt enable register (address 0314h) bit description continued bit symbol description table 59. iso irq mask or register (address 0318h) bit description bit symbol access value description 31 to 0 iso_irq_mask_ or[31:0] r/w 0000 0000h iso irq mask or : represents a direct map for iso ptds 31 to 0. 0 no or condition de?ned between iso ptds. 1 the bits corresponding to certain ptds are set to logic 1 to de?ne a certain or condition. table 60. int irq mask or register (address 031ch) bit description bit symbol access value description 31 to 0 int_irq_mask_ or[31:0] r/w 0000 0000h int irq mask or : represents a direct map for int ptds 31 to 0. 0 no or condition de?ned between int ptds 31 to 0. 1 the bits corresponding to certain ptds are set to logic 1 to de?ne a certain or condition.
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 55 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 8.4.6 iso irq mask and register each bit of this register corresponds to one of the 32 iso ptds de?ned, and is a hardware irq mask for each ptd done map. for details, see section 7.4 . t ab le 62 provides the bit description of the register. 8.4.7 int irq mask and register each bit of this register (see t ab le 63 ) corresponds to one of the 32 int ptds de?ned, and is a hardware irq mask for each ptd done map. for details, see section 7.4 . 8.4.8 atl irq mask and register each bit of this register corresponds to one of the 32 atl ptds de?ned, and is a hardware irq mask for each ptd done map. for details, see section 7.4 . t ab le 64 shows the bit description of the register. table 61. atl irq mask or register (address 0320h) bit description bit symbol access value description 31 to 0 atl_irq_mask _or[31:0] r/w 0000 0000h atl irq mask or : represents a direct map for atl ptds 31 to 0. 0 no or condition de?ned between the atl ptds. 1 the bits corresponding to certain ptds are set to logic 1 to de?ne a certain or condition. table 62. iso irq mask and register (address 0324h) bit description bit symbol access value description 31 to 0 iso_irq_mask _and[31:0] r/w 0000 0000h iso irq mask and : represents a direct map for iso ptds 31 to 0. 0 no and condition de?ned between iso ptds. 1 the bits corresponding to certain ptds are set to logic 1 to de?ne a certain and condition between the 32 int ptds. table 63. int irq mask and register (address 0328h) bit description bit symbol access value description 31 to 0 int_irq_mask _and[31:0] r/w 0000 0000h int irq mask and : represents a direct map for int ptds 31 to 0. 0 no or condition de?ned between int ptds. 1 the bits corresponding to certain ptds are set to logic 1 to de?ne a certain and condition between the 32 int ptds. table 64. atl irq mask and register (address 032ch) bit description bit symbol access value description 31 to 0 atl_irq_mask _and[31:0] r/w 0000 0000h atl irq mask and : represents a direct map for atl ptds 31 to 0. 0 no or condition de?ned between atl ptds. 1 the bits corresponding to certain ptds are set to logic 1 to de?ne a certain and condition between the 32 atl ptds.
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 56 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 9. proprietary transfer descriptor (ptd) the standard ehci data structures as described in ref . 2 enhanced host controller interf ace speci? cation f or univ ersal ser ial bus re v . 1.0 are optimized for the bus master operation that is managed by the hardware state machine. the ptd structures of the saf1760 are translations of the ehci data structures that are optimized for the saf1760. it, however, still follows the basic ehci architecture. this optimized form of ehci data structures is necessary because the saf1760 is a slave host controller and has no bus master capability. ehci manages schedules in two lists: periodic and asynchronous. the data structures are designed to provide the maximum ?exibility required by usb, minimize memory traf?c, and reduce hardware and software complexity. the saf1760 controller executes transactions for devices by using a simple shared-memory schedule. this schedule consists of data structures organized into three lists: qiso isochronous transfer qintl interrupt transfer qatl asynchronous transfer; for the control and bulk transfers the system software maintains two lists for the host controller: periodic and asynchronous. the saf1760 has a maximum of 32 iso, 32 intl and 32 atl ptds. these ptds are used as channels to transfer data from the shared memory to the usb bus. these channels are allocated and de-allocated on receiving the transfer from the core usb driver. multiple transfers are scheduled to the shared memory for various endpoints by traversing the next link pointer provided by endpoint data structures, until it reaches the end of the endpoint list. there are three endpoint lists: one for iso endpoints, and the other for intl and atl endpoints. if the schedule is enabled, the host controller executes the iso schedule, followed by the intl schedule, and then the atl schedule. these lists are traversed and scheduled by the software according to the ehci traversal rule. the host controller executes the scheduled iso, intl and atl ptds. the completion of a transfer is indicated to the software by the interrupt that can be grouped under various ptds by using the and or or registers that are available for each schedule type: iso, intl and atl. these registers are simple logic registers to decide the completion status of group and individual ptds. when the logical conditions of the done bit is true in the shared memory, it means that ptd has completed. there are four types of interrupts in the saf1760: iso, intl, atl and sof. the latency can be programmed in multiples of m sof (125 m s). the nextptd pointer is a feature that allows the saf1760 to jump unused and skip ptds. this will improve the ptd transversal latency time. the nextptd pointer is not meant for same or single endpoint. the nextptd works only in forward direction. the nextptd traversal rules de?ned by the saf1760 hardware are:
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 57 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 1. start the ptd memory vertical traversal, considering the skip and lastptd information, as follows. 2. if the current ptd is active and not done, perform the transaction. 3. follow the nextptd pointer as speci?ed in bits 4 to 0 of dw4. 4. if combined with lastptd, the lastptd setting must be at a higher address than the nextptd speci?ed. both have to be set in a logical manner. 5. if combined with skip, the skip must not be set (logically) on the same position corresponding to nextptd, pointed by the nextptd pointer. 6. if ptd is set for skip, it will be neglected and the next vertical ptd will be considered. 7. if the skipped ptd already has a setting including a nextptd pointer that will not be taken into consideration, the behavior will be just as described in the preceding step. 9.1 high-speed bulk in and out t ab le 65 shows the bit allocation of the high-speed bulk in and out, asynchronous transfer descriptor (td). fig 12. nextptd traversal rule ptd skipped? start ptd schedule no yes check for valid and active bit set? follow next ptd pointed by nextptd pointer no yes start ptd execution is ptd pointer null? go to nextptd vertical yes no 004aaa883
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 58 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller [1] reserved. [2] endpt[0]. table 65. high-speed bulk in and out: bit allocation bit 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 dw7 reserved dw5 reserved dw3 ahbx [1] p dt cerr [1:0] nakcnt[3:0] reserved nrbytestransferred[14:0] (32 kb - 1 b for high-speed) dw1 reserved s ep type [1:0] to k e n [1:0] deviceaddress[6:0] endpt[3:1] bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dw6 reserved dw4 reserved j nextptdpointer[4:0] dw2 reserved rl[3:0] [1] datastartaddress[15:0] reserved dw0 [2] mult [1:0] maxpacketlength[10:0] nrbytestotransfer[14:0] [1] v
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 59 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller table 66. high-speed bulk in and out: bit description bit symbol access value description dw7 63 to 32 reserved - - - dw6 31 to 0 reserved - - - dw5 63 to 32 reserved - - - dw4 31 to 6 reserved - 0 not applicable for asynchronous td 5j sw writes - jump : 0 to increment the ptd pointer. 1 to enable the next ptd branching. 4 to 0 nextptdpointer [4:0] sw writes - next ptd counter : next ptd branching assigned by the ptd pointer. dw3 63 a sw sets hw resets - active : write the same value as that in v. 62 h hw writes - halt : this bit corresponds to the halt bit of the status ?eld of td. 61 b hw writes - babble : this bit corresponds to the babble detected bit in the status ?eld of itd, sitd or td. 1 when babbling is detected, a and v are set to 0. 60 x hw writes - error : this bit corresponds to the transaction error bit in the status ?eld of itd, sitd or td (exec_trans, the signal name is xacterr). 0 no pid error. 1 if there are pid errors, this bit is set active. the a and v bits are also set to inactive. this transaction is retried three times. sw writes - 0 before scheduling. 59 reserved - - - 58 p sw writes hw updates - ping : for high-speed transactions, this bit corresponds to the ping state bit in the status ?eld of a td. 0 ping is not set. 1 ping is set. for the ?rst time, software sets the ping bit to 0. for the successive asynchronous td, software sets the bit in asynchronous td based on the state of the bit for the previous asynchronous td of the same transfer, that is: ? the current asynchronous td is completed with the ping bit set. ? the next asynchronous td will have its ping bit set by the software. 57 dt hw updates sw writes - data toggle : this bit is ?lled by software to start a ptd. if nrbytestotransfer[14:0] is not complete, software needs to read this value and then write back the same value to continue.
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 60 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 56 to 55 cerr[1:0] hw writes sw writes - error counter : this ?eld corresponds to the cerr[1:0] ?eld in td. the default value of this ?eld is zero for isochronous transactions. 00 the transaction will not retry. 11 the transaction will retry three times. hardware will decrement these values. 54 to 51 nakcnt[3:0] hw writes sw writes - nak counter : this ?eld corresponds to the nakcnt ?eld in td. software writes for the initial ptd launch. the v bit is reset if nakcnt decrements to zero and rl is a nonzero value. it reloads from rl if transaction is ack-ed. 50 to 47 reserved - - - 46 to 32 nrbytes transferred [14:0] hw writes sw writes - number of bytes transferred : this ?eld indicates the number of bytes sent or received for this transaction. if mult[1:0] is greater than one, it is possible to store intermediate results in this ?eld. dw2 31 to 29 reserved - - set to logic 0 for asynchronous td. 28 to 25 rl[3:0] sw writes - reload : if rl is set to 0h, hardware ignores the nakcnt value. rl and nakcnt are set to the same value before a transaction. 24 reserved - - always logic 0 for asynchronous td. 23 to 8 datastart address[15:0] sw writes - data start address : this is the start address for data that will be sent or received on or from the usb bus. this is the internal memory address and not the direct cpu address. ram address = (cpu address - 400h) / 8 7 to 0 reserved - - - dw1 63 to 47 reserved - - always logic 0 for asynchronous td. 46 s sw writes - this bit indicates whether a split transaction has to be executed: 0 high-speed transaction 1 split transaction 45 to 44 eptype[1:0] sw writes - transaction type: 00 control 10 bulk 43 to 42 token[1:0] sw writes - token : identi?es the token packet identi?er (pid) for this transaction: 00 out 01 in 10 setup 11 ping (written by hardware only). 41 to 35 deviceaddress [6:0] sw writes - device address : this is the usb address of the function containing the endpoint that is referred to by this buffer. 34 to 32 endpt[3:1] sw writes - endpoint : this is the usb address of the endpoint within the function. table 66. high-speed bulk in and out: bit description continued bit symbol access value description
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 61 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 9.2 high-speed isochronous in and out t ab le 67 shows the bit allocation of the high-speed isochronous in and out, isochronous transfer descriptor (itd). dw0 31 endpt[0] sw writes - endpoint : this is the usb address of the endpoint within the function. 30 to 29 mult[1:0] sw writes - multiplier : this ?eld is a multiplier used by the host controller as the number of successive packets the host controller may submit to the endpoint in the current execution. set this ?eld to 01b. you can also set it to 11b and 10b depending on your application. 00b is unde?ned. 28 to 18 maxpacket length[10:0] sw writes - maximum packet length : this ?eld indicates the maximum number of bytes that can be sent to or received from an endpoint in a single data packet. the maximum packet size for a bulk transfer is 512 bytes. the maximum packet size for the isochronous transfer is also variable at any whole number. 17 to 3 nrbytesto transfer[14:0] sw writes - number of bytes to transfer : this ?eld indicates the number of bytes that can be transferred by this data structure. it is used to indicate the depth of the data ?eld (32 kb - 1 b). 2 to 1 reserved - - - 0v sw sets hw resets - valid : 0 this bit is deactivated when the entire ptd is executed, or when a fatal error is encountered. 1 software updates to one when there is payload to be sent or received. the current ptd is active. table 66. high-speed bulk in and out: bit description continued bit symbol access value description
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 62 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller [1] reserved. [2] endpt[0]. table 67. high-speed isochronous in and out: bit allocation bit 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 dw7 isoin_7[11:0] isoin_6[11:0] isoin_5[11:4] dw5 isoin_2[7:0] isoin_1[11:0] isoin_0[11:0] dw3 a h b reserved nrbytestransferred[14:0] (32 kb - 1 b for high-speed) dw1 reserved s ep type [1:0] to k e n [1:0] deviceaddress[6:0] endpt[3:1] bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dw6 isoin_5[3:0] isoin_4[11:0] isoin_3[11:0] isoin_2[11:8] dw4 status7[2:0] status6[2:0] status5[2:0] status4[2:0] status3[2:0] status2[2:0] status1[2:0] status0[2:0] m sa[7:0] dw2 reserved datastartaddress[15:0] m frame[7:0] dw0 [2] mult [1:0] maxpacketlength[10:0] nrbytestotransfer[14:0] [1] v
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 63 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller table 68. high-speed isochronous in and out: bit description bit symbol access value description dw7 63 to 52 isoin_7[11:0] hw writes - bytes received during m sof7, if m sa[7] is set to 1 and frame number is correct. 51 to 40 isoin_6[11:0] hw writes - bytes received during m sof6, if m sa[6] is set to 1 and frame number is correct. 39 to 32 isoin_5[11:4] hw writes - bytes received during m sof5 (bits 11 to 4), if m sa[5] is set to 1 and frame number is correct. dw6 31 to 28 isoin_5[3:0] hw writes - bytes received during m sof5 (bits 3 to 0), if m sa[5] is set to 1 and frame number is correct. 27 to 16 isoin_4[11:0] hw writes - bytes received during m sof4, if m sa[4] is set to 1 and frame number is correct. 15 to 4 isoin_3[11:0] hw writes - bytes received during m sof3, if m sa[3] is set to 1 and frame number is correct. 3 to 0 isoin_2[11:8] hw writes - bytes received during m sof2 (bits 11 to 8), if m sa[2] is set to 1 and frame number is correct. dw5 63 to 56 isoin_2[7:0] hw writes - bytes received during m sof2 (bits 7 to 0), if m sa[2] is set to 1 and frame number is correct. 55 to 44 isoin_1[11:0] hw writes - bytes received during m sof1, if m sa[1] is set to 1 and frame number is correct. 43 to 32 isoin_0[11:0] hw writes - bytes received during m sof0, if m sa[0] is set to 1 and frame number is correct. dw4 31 to 29 status7[2:0] hw writes - iso in or out status at m sof7 28 to 26 status6[2:0] hw writes - iso in or out status at m sof6 25 to 23 status5[2:0] hw writes - iso in or out status at m sof5 22 to 20 status4[2:0] hw writes - iso in or out status at m sof4 19 to 17 status3[2:0] hw writes - iso in or out status at m sof3 16 to 14 status2[2:0] hw writes - iso in or out status at m sof2 13 to 11 status1[2:0] hw writes - iso in or out status at m sof1 10 to 8 status0[2:0] hw writes - status of the payload on the usb bus for this m sof after iso has been delivered. bit 0 transaction error (in and out) bit 1 babble (in token only) bit 2 underrun (out token only) 7to0 m sa[7:0] sw writes (0 ? 1) hw writes (1 ? 0) after processing - m sof active : when the frame number of bits dw1[7:3] match the frame number of the usb bus, these bits are checked for 1 before they are sent for m sof. for example: if m sa[7:0] = 1111 1111b: send iso every m sof of the entire millisecond. if m sa[7:0] = 0101 0101b: send iso only on m sof0, m sof2, m sof4 and m sof6.
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 64 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller dw3 63 a sw sets - active : this bit is the same as the valid bit. 62 h hw writes - halt : only one bit for the entire millisecond. when this bit is set, the valid bit is reset. the device decides to stall an endpoint. 61 b hw writes - babble : not applicable here. 60 to 47 reserved - 0 set to 0 for isochronous. 46 to 32 nrbytes transferred [14:0] hw writes - number of bytes transferred : this ?eld indicates the number of bytes sent or received for this transaction. if mult[1:0] is greater than one, it is possible to store intermediate results in this ?eld. nrbytestransferred[14:0] is 32 kb - 1 b per ptd. dw2 31 to 24 reserved - 0 set to 0 for isochronous. 23 to 8 datastart address[15:0] sw writes - data start address : this is the start address for data that will be sent or received on or from the usb bus. this is the internal memory address and not the direct cpu address. ram address = (cpu address - 400h) / 8 7to0 m frame[7:0] sw writes - bits 2 to 0 dont care bits 7 to 3 frame number that this ptd will be sent for iso out or in dw1 63 to 47 reserved - - - 46 s sw writes - this bit indicates whether a split transaction has to be executed. 0 high-speed transaction 1 split transaction 45 to 44 eptype[1:0] sw writes - endpoint type : 01 isochronous 43 to 42 token[1:0] sw writes - token : this ?eld indicates the token pid for this transaction: 00 out 01 in 41 to 35 device address[6:0] sw writes - device address : this is the usb address of the function containing the endpoint that is referred to by this buffer. 34 to 32 endpt[3:1] sw writes - endpoint : this is the usb address of the endpoint within the function. table 68. high-speed isochronous in and out: bit description continued bit symbol access value description
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 65 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 9.3 high-speed interrupt in and out t ab le 69 shows the bit allocation of the high-speed interrupt in and out, periodic transfer descriptor (ptd). dw0 31 endpt[0] sw writes - endpoint : this is the usb address of the endpoint within the function. 30 to 29 mult[1:0] sw writes - this ?eld is a multiplier counter used by the host controller as the number of successive packets the host controller may submit to the endpoint in the current execution. for details, refer to appendix d of ref . 2 enhanced host controller interf ace speci? cation f or univ ersal ser ial bus re v . 1.0 . 28 to 18 maxpacket length[10:0] sw writes - maximum packet length : this ?eld indicates the maximum number of bytes that can be sent to or received from the endpoint in a single data packet. the maximum packet size for an isochronous transfer is 1024 bytes. the maximum packet size for the isochronous transfer is also variable at any whole number. 17 to 3 nrbytesto transfer[14:0] sw writes - number of bytes transferred : this ?eld indicates the number of bytes that can be transferred by this data structure. it is used to indicate the depth of the data ?eld (32 kb - 1 b). 2 to 1 reserved - - - 0v hw resets sw sets - 0 this bit is deactivated when the entire ptd is executed, or when a fatal error is encountered. 1 software updates to one when there is payload to be sent or received. the current ptd is active. table 68. high-speed isochronous in and out: bit description continued bit symbol access value description
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 66 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller [1] reserved. [2] endpt[0]. table 69. high-speed interrupt in and out: bit allocation bit 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 dw7 int_in_7[11:0] int_in_6[11:0] int_in_5[11:4] dw5 int_in_2[7:0] int_in_1[11:0] int_in_0[11:0] dw3 a h reserved dt cerr [1:0] reserved nrbytestransferred[14:0] (32 kb - 1 b for high-speed) dw1 reserved s ep type [1:0] to k e n [1:0] deviceaddress[6:0] endpt[3:1] bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dw6 int_in_5[3:0] int_in_4[11:0] int_in_3[11:0] int_in_2[11:8] dw4 status7[2:0] status6[2:0] status5[2:0] status4[2:0] status3[2:0] status2[2:0] status1[2:0] status0[2:0] m sa[7:0] dw2 reserved datastartaddress[15:0] m frame[7:0] dw0 [2] mult [1:0] maxpacketlength[10:0] nrbytestotransfer[14:0] [1] v
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 67 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller table 70. high-speed interrupt in and out: bit description bit symbol access value description dw7 63 to 52 int_in_7[11:0] hw writes - bytes received during m sof7, if m sa[7] is set to 1 and frame number is correct. 51 to 40 int_in_6[11:0] hw writes - bytes received during m sof6, if m sa[6] is set to 1 and frame number is correct. 39 to 32 int_in_5[11:4] hw writes - bytes received during m sof5 (bits 11 to 4), if m sa[5] is set to 1 and frame number is correct. dw6 31 to 28 int_in_5[3:0] hw writes - bytes received during m sof5 (bits 3 to 0), if m sa[5] is set to 1 and frame number is correct. 27 to 16 int_in_4[11:0] hw writes - bytes received during m sof4, if m sa[4] is set to 1 and frame number is correct. 15 to 4 int_in_3[11:0] hw writes - bytes received during m sof3, if m sa[3] is set to 1 and frame number is correct. 3 to 0 int_in_2[11:8] hw writes - bytes received during m sof2 (bits 11 to 8), if m sa[2] is set to 1 and frame number is correct. dw5 63 to 56 int_in_2[7:0] hw writes - bytes received during m sof2 (bits 7 to 0), if m sa[2] is set to 1 and frame number is correct. 55 to 44 int_in_1[11:0] hw writes - bytes received during m sof1, if m sa[1] is set to 1 and frame number is correct. 43 to 32 int_in_0[11:0] hw writes - bytes received during m sof0, if m sa[0] is set to 1 and frame number is correct. dw4 31 to 29 status7[2:0] hw writes - int in or out status of m sof7 28 to 26 status6[2:0] hw writes - int in or out status of m sof6 25 to 23 status5[2:0] hw writes - int in or out status of m sof5 22 to 20 status4[2:0] hw writes - int in or out status of m sof4 19 to 17 status3[2:0] hw writes - int in or out status of m sof3 16 to 14 status2[2:0] hw writes - int in or out status of m sof2 13 to 11 status1[2:0] hw writes - int in or out status of m sof1 10 to 8 status0[2:0] hw writes - status of the payload on the usb bus for this m sof after int has been delivered. bit 0 transaction error (in and out) bit 1 babble (in token only) bit 2 underrun (out token only) 7to0 m sa[7:0] sw writes (0 ? 1) hw writes (1 ? 0) after processing - when the frame number of bits dw2[7:3] match the frame number of the usb bus, these bits are checked for 1 before they are sent for m sof. for example: when m sa[7:0] = 1111 1111b: send int for every m sof of the entire millisecond. when m sa[7:0] = 0101 0101b: send int for m sof0, m sof2, m sof4 and m sof6. when m sa[7:0] = 1000 1000b: send int for every fourth m sof.
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 68 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller dw3 63 a hw writes sw writes - active : write the same value as that in v. 62 h hw writes - halt : transaction is halted. 61 to 58 reserved - - - 57 dt hw writes sw writes - data toggle : set the data toggle bit to start the ptd. software writes the current transaction toggle value. hardware writes the next transaction toggle value. 56 to 55 cerr[1:0] hw writes sw writes - error counter . this ?eld corresponds to the cerr[1:0] ?eld in the td. the default value of this ?eld is zero for isochronous transactions. 54 to 47 reserved - - - 46 to 32 nrbytes transferred [14:0] hw writes - number of bytes transferred : this ?eld indicates the number of bytes sent or received for this transaction. if mult[1:0] is greater than one, it is possible to store intermediate results in this ?eld. dw2 31 to 24 reserved - - - 23 to 8 datastart address[15:0] sw writes - data start address : this is the start address for data that will be sent or received on or from the usb bus. this is the internal memory address and not the direct cpu address. ram address = (cpu address - 400h) / 8 7to0 m frame[7:0] sw writes - bits 7 to 3 represent the polling rate in milliseconds. the int polling rate is de?ned as 2 (b - 1) m sof, where b is 1 to 9. when b is 1, 2, 3 or 4, use m sa to de?ne polling because the rate is equal to or less than 1 ms. bits 7 to 3 are set to 0. polling checks m sa bits for m sof rates. see t ab le 71 . dw1 63 to 47 reserved - - - 46 s sw writes - this bit indicates if a split transaction has to be executed: 0 high-speed transaction 1 split transaction 45 to 44 eptype[1:0] sw writes - endpoint type : 11 interrupt 43 to 42 token[1:0] sw writes - token : this ?eld indicates the token pid for this transaction: 00 out 01 in 41 to 35 deviceaddress [6:0] sw writes - device address : this is the usb address of the function containing the endpoint that is referred to by the buffer. 34 to 32 endpt[3:1] sw writes - endpoint : this is the usb address of the endpoint within the function. table 70. high-speed interrupt in and out: bit description continued bit symbol access value description
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 69 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 9.4 start and complete split for bulk t ab le 72 shows the bit allocation of start split (ss) and complete split (cs) for bulk, asynchronous start split and complete split (ss/cs) transfer descriptor (td). dw0 31 endpt[0] sw writes - endpoint : this is the usb address of the endpoint within the function. 30 to 29 mult[1:0] sw writes - multiplier : this ?eld is a multiplier counter used by the host controller as the number of successive packets the host controller may submit to the endpoint in the current execution. set this ?eld to 01b. you can also set it to 11b and 10b, depending on your application. 00b is unde?ned. 28 to 18 maxpacket length[10:0] sw writes - maximum packet length : this ?eld indicates the maximum number of bytes that can be sent to or received from the endpoint in a single data packet. 17 to 3 nrbytesto transfer[14:0] sw writes - number of bytes to transfer : this ?eld indicates the number of bytes that can be transferred by this data structure. it is used to indicate the depth of the data ?eld (32 kb - 1 b). 2 to 1 reserved - - - 0v sw sets hw resets - valid : 0 this bit is deactivated when the entire ptd is executed, or when a fatal error is encountered. 1 software updates to one when there is payload to be sent or received. the current ptd is active. table 70. high-speed interrupt in and out: bit description continued bit symbol access value description table 71. microframe description b rate m frame[7:3] m sa[7:0] 11 m sof 0 0000b 1111 1111b 22 m sof 0 0000b 1010 1010b or 0101 0101b 34 m sof 0 0000b any 2 bits set 4 1 ms 0 0000b any 1 bit set 5 2 ms 0 0001b any 1 bit set 6 4 ms 0 0010b to 0 0011b any 1 bit set 7 8 ms 0 0100b to 0 0111b any 1 bit set 8 16 ms 0 1000b to 0 1111b any 1 bit set 9 32 ms 1 0000b to 1 1111b any 1 bit set
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 70 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller [1] reserved. [2] endpt[0]. table 72. start and complete split for bulk: bit allocation bit 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 dw7 reserved dw5 reserved dw3 ahbxsc [1] dt cerr [1:0] nakcnt[3:0] reserved nrbytestransferred[14:0] dw1 hubaddress[6:0] portnumber[6:0] se[1:0] [1] sep type [1:0] to k e n [1:0] deviceaddress[6:0] endpt[3:1] bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dw6 reserved dw4 reserved j nextptdaddress[4:0] dw2 reserved rl[3:0] [1] datastartaddress[15:0] reserved dw0 [2] [1] maxpacketlength[10:0] nrbytestotransfer[14:0] [1] v
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 71 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller table 73. start and complete split for bulk: bit description bit symbol access value description dw7 63 to 32 reserved - - - dw6 31 to 0 reserved - - - dw5 63 to 32 reserved - - - dw4 31 to 6 reserved - - - 5j sw writes - 0 to increment the ptd pointer. 1 to enable the next ptd branching. 4 to 0 nextptdpointer[4:0] sw writes - next ptd branching assigned by the ptd pointer. dw3 63 a sw sets hw resets - active : write the same value as that in v. 62 h hw writes - halt : this bit corresponds to the halt bit of the status ?eld of td. 61 b hw writes - babble : this bit corresponds to the babble detected bit in the status ?eld of itd, sitd or td. 1 when babbling is detected, a and v are set to 0. 60 x hw writes - transaction error : this bit corresponds to the transaction error bit in the status ?eld. sw writes - 0 before scheduling 59 sc sw writes 0 hw updates - start/complete : 0 start split 1 complete split 58 reserved - - - 57 dt hw writes sw writes - data toggle : set the data toggle bit to start for the ptd. 56 to 55 cerr[1:0] hw updates sw writes - error counter : this ?eld contains the error count for asynchronous start and complete split (ss/cs) td. when an error has no response or bad response, cerr[1:0] will be decremented to zero and then valid will be set to zero. a nak or nyet will reset cerr[1:0]. for details, refer to section 4.12.1.2 of ref . 2 enhanced host controller interf ace speci? cation f or univ ersal ser ial bus re v . 1.0 . if retry has insuf?cient time at the beginning of a new sof, the ?rst ptd must be this retry. this can be accomplished if aperiodic ptd is not advanced. 54 to 51 nakcnt[3:0] hw writes sw writes - nak counter : the v bit is reset if nakcnt decrements to zero and rl is a nonzero value. not applicable to isochronous split transactions. 50 to 47 reserved - - - 46 to 32 nrbytes transferred[14:0] hw writes - number of bytes transferred : this ?eld indicates the number of bytes sent or received for this transaction.
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 72 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller dw2 31 to 29 reserved - - - 28 to 25 rl[3:0] sw writes - reload : if rl is set to 0h, hardware ignores the nakcnt value. set rl and nakcnt to the same value before a transaction. for full-speed and low-speed transactions, set this ?eld to 0000b. not applicable to isochronous start split and complete split. 24 reserved - - - 23 to 8 datastartaddress [15:0] sw writes - data start address : this is the start address for data that will be sent or received on or from the usb bus. this is the internal memory address and not the direct cpu address. ram address = (cpu address - 400h) / 8 7 to 0 reserved - - - dw1 63 to 57 hubaddress[6:0] sw writes - hub address : this indicates the hub address. 56 to 50 portnumber[6:0] sw writes - port number : this indicates the port number of the hub or embedded tt. 49 to 48 se[1:0] sw writes - this depends on the endpoint type and direction. it is valid only for split transactions. t ab le 74 applies to start split and complete split only. 47 reserved - - - 46 s sw writes - this bit indicates whether a split transaction has to be executed: 0 high-speed transaction 1 split transaction 45 to 44 eptype[1:0] sw writes - endpoint type : 00 control 10 bulk 43 to 42 token[1:0] sw writes - token : this ?eld indicates the pid for this transaction. 00 out 01 in 10 setup 41 to 35 deviceaddress[6:0] sw writes - device address : this is the usb address of the function containing the endpoint that is referred to by this buffer. 34 to 32 endpt[3:1] sw writes - endpoint : this is the usb address of the endpoint within the function. table 73. start and complete split for bulk: bit description continued bit symbol access value description
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 73 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 9.5 start and complete split for isochronous t ab le 75 shows the bit allocation for start and complete split for isochronous, split isochronous transfer descriptor (sitd). dw0 31 endpt[0] sw writes - endpoint : this is the usb address of the endpoint within the function. 30 to 29 reserved - - - 28 to 18 maximumpacket length[10:0] sw writes - maximum packet length : this ?eld indicates the maximum number of bytes that can be sent to or received from an endpoint in a single data packet. the maximum packet size for full-speed is 64 bytes as de?ned in the ref . 1 univ ersal ser ial bus speci? cation re v . 2.0 . 17 to 3 nrbytestotransfer [14:0] sw writes - number of bytes to transfer : this ?eld indicates the number of bytes that can be transferred by this data structure. it is used to indicate the depth of the data ?eld. 2 to 1 reserved - - - 0v sw sets hw resets - valid : 0 this bit is deactivated when the entire ptd is executed, or when a fatal error is encountered. 1 software updates to one when there is payload to be sent or received. the current ptd is active. table 73. start and complete split for bulk: bit description continued bit symbol access value description table 74. se description bulk control s e remarks i/o i/o 1 0 low-speed i/o i/o 0 0 full-speed
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 74 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller [1] reserved. [2] endpt[0]. table 75. start and complete split for isochronous: bit allocation bit 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 dw7 reserved iso_in_7[7:0] dw5 iso_in_2[7:0] iso_in_1[7:0] iso_in_0[7:0] m scs[7:0] [2] dw3 ahbxsc [1] dt reserved nrbytestransferred[11:0] dw1 hubaddress[6:0] portnumber[6:0] reserved s ep type [1:0] to k e n [1:0] deviceaddress[6:0] endpt[3:1] bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dw6 iso_in_6[7:0] iso_in_5[7:0] iso_in_4[7:0] iso_in_3[7:0] dw4 status7[2:0] status6[2:0] status5[2:0] status4[2:0] status3[2:0] status2[2:0] status1[2:0] status0[2:0] m sa[7:0] dw2 reserved datastartaddress[15:0] m frame[7:0] (full-speed) dw0 [2] [1] tt_mps_len[10:0] nrbytestotransfer[14:0] (1 kb for full-speed) [1] v
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 75 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller table 76. start and complete split for isochronous: bit description bit symbol access value description dw7 63 to 40 reserved - - - 39 to 32 iso_in_7[7:0] hw writes - bytes received during m sof7, if m sa[7] is set to 1 and frame number is correct. dw6 31 to 24 iso_in_6[7:0] hw writes - bytes received during m sof6, if m sa[6] is set to 1 and frame number is correct. 23 to 16 iso_in_5[7:0] hw writes - bytes received during m sof5, if m sa[5] is set to 1 and frame number is correct. 15 to 8 iso_in_4[7:0] hw writes - bytes received during m sof4, if m sa[4] is set to 1 and frame number is correct. 7 to 0 iso_in_3[7:0] hw writes - bytes received during m sof3, if m sa[3] is set to 1 and frame number is correct. dw5 63 to 56 iso_in_2[7:0] hw writes - bytes received during m sof2 (bits 7 to 0), if m sa[2] is set to 1 and frame number is correct. 55 to 48 iso_in_1[7:0] hw writes - bytes received during m sof1, if m sa[1] is set to 1 and frame number is correct. 47 to 40 iso_in_0[7:0] hw writes - bytes received during m sof0 if m sa[0] is set to 1 and frame number is correct. 39 to 32 m scs[7:0] sw writes (0 ? 1) hw writes (1 ? 0) after processing - all bits can be set to one for every transfer. it speci?es which m sof the complete split needs to be sent. valid only for in. start split and complete split active bits, m sa = 0000 0001b, m scs = 0000 0100b, will cause ss to execute in m frame0 and cs in m frame2. dw4 31 to 29 status7[2:0] hw writes - isochronous in or out status of m sof7 28 to 26 status6[2:0] hw writes - isochronous in or out status of m sof6 25 to 23 status5[2:0] hw writes - isochronous in or out status of m sof5 22 to 20 status4[2:0] hw writes - isochronous in or out status of m sof4 19 to 17 status3[2:0] hw writes - isochronous in or out status of m sof3 16 to 14 status2[2:0] hw writes - isochronous in or out status of m sof2 13 to 11 status1[2:0] hw writes - isochronous in or out status of m sof1 10 to 8 status0[2:0] hw writes - isochronous in or out status of m sof0 bit 0 transaction error (in and out) bit 1 babble (in token only) bit 2 underrun (out token only) 7to0 m sa[7:0] sw writes (0 ? 1) hw writes (1 ? 0) after processing - speci?es which m sof the start split needs to be placed. for out token : when the frame number of bits dw2[7:3] matches the frame number of the usb bus, these bits are checked for one before they are sent for the m sof. for in token : only m sof0, m sof1, m sof2 or m sof3 can be set to 1. nothing can be set for m sof4 and above.
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 76 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller dw3 63 a sw sets hw resets - active : write the same value as that in v. 62 h hw writes - halt : the halt bit is set when any microframe transfer status has a stalled or halted condition. 61 b hw writes - babble : this bit corresponds to bit 1 of status0 to status7 for every microframe transfer status. 60 x hw writes - transaction error : this bit corresponds to bit 0 of status0 to status7 for every microframe transfer status. 59 sc sw writes 0 hw updates - start/complete : 0 start split 1 complete split 58 reserved - - - 57 dt hw writes sw writes - data toggle : set the data toggle bit to start for the ptd. 56 to 44 reserved - - - 43 to 32 nrbytes transferred[11:0] hw writes - number of bytes transferred : this ?eld indicates the number of bytes sent or received for this transaction. dw2 31 to 24 reserved - - - 23 to 8 datastart address[15:0] sw writes - data start address : this is the start address for data that will be sent or received on or from the usb bus. this is the internal memory address and not the cpu address. 7to0 m frame[7:0] sw writes - bits 7 to 3 determine which frame to execute. dw1 63 to 57 hubaddress [6:0] sw writes - hub address : this indicates the hub address. 56 to 50 portnumber [6:0] sw writes - port number : this indicates the port number of the hub or embedded tt. 49 to 47 reserved - - - 46 s sw writes - this bit indicates whether a split transaction has to be executed: 0 high-speed transaction 1 split transaction 45 to 44 eptype[1:0] sw writes - transaction type: 01 isochronous 43 to 42 token[1:0] sw writes - token pid for this transaction: 00 out 01 in 41 to 35 deviceaddress [6:0] sw writes - device address : this is the usb address of the function containing the endpoint that is referred to by this buffer. 34 to 32 endpt[3:1] sw writes - endpoint : this is the usb address of the endpoint within the function. table 76. start and complete split for isochronous: bit description continued bit symbol access value description
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 77 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 9.6 start and complete split for interrupt t ab le 77 shows the bit allocation of start and complete split for interrupt. dw0 31 endpt[0] sw writes - endpoint : this is the usb address of the endpoint within the function. 30 to 29 reserved - - - 28 to 18 tt_mps_len [10:0] sw writes - transaction translator maximum packet size length : this ?eld indicates the maximum number of bytes that can be sent per start split, depending on the number of total bytes needed. if the total bytes to be sent for the entire millisecond is greater than 188 bytes, this ?eld should be set to 188 bytes for an out token and 192 bytes for an in token. otherwise, this ?eld should be equal to the total bytes sent. 17 to 3 nrbytesto transfer[14:0] sw writes - number of bytes to transfer : this ?eld indicates the number of bytes that can be transferred by this data structure. it is used to indicate the depth of the data ?eld. this ?eld is restricted to 1023 bytes because in sitd the maximum allowable payload for a full-speed device is 1023 bytes. this ?eld indirectly becomes the maximum packet size of the downstream device. 2 to 1 reserved - - - 0v sw sets hw resets - 0 this bit is deactivated when the entire ptd is executed, or when a fatal error is encountered. 1 software updates to one when there is payload to be sent or received. the current ptd is active. table 76. start and complete split for isochronous: bit description continued bit symbol access value description
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 78 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller [1] reserved. [2] endpt[0]. table 77. start and complete split for interrupt: bit allocation bit 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 dw7 reserved int_in_7[7:0] dw5 int_in_2[7:0] int_in_1[7:0] int_in_0[7:0] m scs[7:0] dw3 ahbxsc [1] dt cerr [1:0] reserved nrbytestransferred[11:0] (4 kb for full-speed and low-speed) dw1 hubaddress[6:0] portnumber[6:0] se[1:0] [1] sep type [1:0] to k e n [1:0] deviceaddress[6:0] endpt[3:1] bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dw6 int_in_6[7:0] int_in_5[7:0] int_in_4[7:0] int_in_3[7:0] dw4 status7[2:0] status6[2:0] status5[2:0] status4[2:0] status3[2:0] status2[2:0] status1[2:0] status0[2:0] m sa[7:0] dw2 reserved datastartaddress[15:0] m frame[7:0] (full-speed and low-speed) dw0 [2] [1] maxpacketlength[10:0] nrbytestotransfer[14:0] (4 kb for full-speed and low-speed) [1] v
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 79 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller table 78. start and complete split for interrupt: bit description bit symbol access value description dw7 63 to 40 reserved - - - 39 to 32 int_in_7[7:0] hw writes - bytes received during m sof7, if m sa[7] is set to 1 and frame number is correct. the new value continuously overwrites the old value. dw6 31 to 24 int_in_6[7:0] hw writes - bytes received during m sof6, if m sa[6] is set to 1 and frame number is correct. the new value continuously overwrites the old value. 23 to 16 int_in_5[7:0] hw writes - bytes received during m sof5, if m sa[5] is set to 1 and frame number is correct. the new value continuously overwrites the old value. 15 to 8 int_in_4[7:0] hw writes - bytes received during m sof4, if m sa[4] is set to 1 and frame number is correct. the new value continuously overwrites the old value. 7 to 0 int_in_3[7:0] hw writes - bytes received during m sof3, if m sa[3] is set to 1 and frame number is correct. the new value continuously overwrites the old value. dw5 63 to 56 int_in_2[7:0] hw writes - bytes received during m sof2 (bits 7 to 0), if m sa[2] is set to 1 and frame number is correct. the new value continuously overwrites the old value. 55 to 48 int_in_1[7:0] hw writes - bytes received during m sof1, if m sa[1] is set to 1 and frame number is correct. the new value continuously overwrites the old value. 47 to 40 int_in_0[7:0] hw writes - bytes received during m sof0 if m sa[0] is set to 1 and frame number is correct. the new value continuously overwrites the old value. 39 to 32 m scs[7:0] sw writes (0 ? 1) hw writes (1 ? 0) after processing - all bits can be set to one for every transfer. it speci?es which m sof the complete split needs to be sent. valid only for in. start split and complete split active bits, m sa = 0000 0001, m scs = 0000 0100, will cause ss to execute in m frame0 and cs in m frame2. dw4 31 to 29 status7[2:0] hw writes - interrupt in or out status of m sof7 28 to 26 status6[2:0] hw writes - interrupt in or out status of m sof6 25 to 23 status5[2:0] hw writes - interrupt in or out status of m sof5 22 to 20 status4[2:0] hw writes - interrupt in or out status of m sof4 19 to 17 status3[2:0] hw writes - interrupt in or out status of m sof3 16 to 14 status2[2:0] hw writes - interrupt in or out status of m sof2 13 to 11 status1[2:0] hw writes - interrupt in or out status of m sof1 10 to 8 status0[2:0] hw writes - interrupt in or out status of m sof0 bit 0 transaction error (in and out) bit 1 babble (in token only) bit 2 underrun (out token only)
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 80 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 7to0 m sa[7:0] sw writes (0 ? 1) hw writes (1 ? 0) after processing - speci?es which m sof the start split needs to be placed. for out token : when the frame number of bits dw1[7:3] matches the frame number of the usb bus, these bits are checked for one before they are sent for the m sof. for in token : only m sof0, m sof1, m sof2 or m sof3 can be set to 1. nothing can be set for m sof4 and above. dw3 63 a sw sets hw resets - active : write the same value as that in v. 62 h hw writes - halt : the halt bit is set when any microframe transfer status has a stalled or halted condition. 61 b hw writes - babble : this bit corresponds to bit 1 of status0 to status7 for every microframe transfer status. 60 x hw writes - transaction error : this bit corresponds to bit 0 of status0 to status7 for every microframe transfer status. 59 sc sw writes 0 hw updates - start/complete : 0 start split 1 complete split 58 reserved - - - 57 dt hw writes sw writes - data toggle : for an interrupt transfer, set correct bit to start the ptd. 56 to 55 cerr[1:0] hw writes sw writes - error counter : this ?eld corresponds to the cerr[1:0] ?eld in td. 00 the transaction will not retry. 11 the transaction will retry three times. hardware will decrement these values. 54 to 44 reserved - - - 43 to 32 nrbytes transferred[11:0] hw writes - number of bytes transferred : this ?eld indicates the number of bytes sent or received for this transaction. dw2 31 to 24 reserved - - - 23 to 8 datastart address[15:0] sw writes - data start address : this is the start address for data that will be sent or received on or from the usb bus. this is the internal memory address and not the cpu address. 7to0 m frame[7:0] sw writes - bits 7 to 3 is the polling rate in milliseconds. polling rate is de?ned as 2 (b - 1) m sof; where b = 4 to 16. when b is 4, executed every millisecond. see t ab le 79 . dw1 63 to 57 hubaddress [6:0] sw writes - hub address : this indicates the hub address. 56 to 50 portnumber[6:0] sw writes - port number : this indicates the port number of the hub or embedded tt. 49 to 48 se[1:0] sw writes - this depends on the endpoint type and direction. it is valid only for split transactions. t ab le 80 applies to start split and complete split only. 47 reserved - - - table 78. start and complete split for interrupt: bit description continued bit symbol access value description
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 81 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 46 s sw writes - this bit indicates whether a split transaction has to be executed: 0 high-speed transaction 1 split transaction 45 to 44 eptype[1:0] sw writes - transaction type: 11 interrupt 43 to 42 token[1:0] sw writes - token pid for this transaction: 00 out 01 in 41 to 35 deviceaddress [6:0] sw writes - device address : this is the usb address of the function containing the endpoint that is referred to by this buffer. 34 to 32 endpt[3:1] sw writes - endpoint : this is the usb address of the endpoint within the function. dw0 31 endpt[0] sw writes - endpoint : this is the usb address of the endpoint within the function. 30 to 29 reserved - - - 28 to 18 maxpacketlength [10:0] sw writes - maximum packet length : this ?eld indicates the maximum number of bytes that can be sent to or received from an endpoint in a single data packet. the maximum packet size for the full-speed and low-speed devices is 64 bytes as de?ned in ref . 1 univ ersal ser ial bus speci? cation re v . 2.0 . 17 to 3 nrbytesto transfer[14:0] sw writes - number of bytes to transfer : this ?eld indicates the number of bytes that can be transferred by this data structure. it is used to indicate the depth of the data ?eld. the maximum total number of bytes for this transaction is 4 kb. 2 to 1 reserved - - - 0v sw sets hw resets - 0 this bit is deactivated when the entire ptd is executed, or when a fatal error is encountered. 1 software updates to one when there is payload to be sent or received. the current ptd is active. table 78. start and complete split for interrupt: bit description continued bit symbol access value description table 79. microframe description b rate m frame[7:3] 5 2 ms 0 0001b 6 4 ms 0 0010b or 0 0011b 7 8 ms 0 0100b or 0 0111b 8 16 ms 0 1000b or 0 1111b 9 32 ms 1 0000b or 1 1111b table 80. se description interrupt s e remarks i/o 1 0 low-speed i/o 0 0 full-speed
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 82 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 10. power consumption the idle operating current, i cc , that is, when the saf1760 is in operational mode, initialized and without any devices connected, is 70 ma. the additional current consumption on i cc is below 1 ma per port in the case of full-speed and low-speed devices. deep-sleep suspend mode ensures the lowest power consumption when v cc(5v0) is always supplied to the saf1760. the suspend current i cc(susp) is typically about 150 m a at room temperature. the suspend current may increase if the ambient temperature increases. for details, see section 7.6 . in hybrid mode, when v cc(5v0) is disconnected, i cc(i/o) will generally be below 100 m a. the average value is 60 m a to 70 m a. under the condition of constant read and write accesses occurring on the 32-bit data bus, the maximum i cc(i/o) drawn from v cc(i/o) is measured as 25 ma when the nxp saf1760 evaluation board is connected to a bsquare pxa255 development platform. this current will vary depending on the platform because of the different access timing, the type of data patterns written on the data bus, and loading on the data bus. table 81. power consumption number of ports working i cc one port working (high-speed) v cc(5v0) = 5.0 v, v cc(i/o) = 3.3 v 90 ma v cc(5v0) = 3.3 v, v cc(i/o) = 3.3 v 77 ma v cc(5v0) = 5.0 v, v cc(i/o) = 1.8 v 82 ma v cc(5v0) = 3.3 v, v cc(i/o) = 1.8 v 77 ma two ports working (high-speed) v cc(5v0) = 5.0 v, v cc(i/o) = 3.3 v 110 ma v cc(5v0) = 3.3 v, v cc(i/o) = 3.3 v 97 ma v cc(5v0) = 5.0 v, v cc(i/o) = 1.8 v 102 ma v cc(5v0) = 3.3 v, v cc(i/o) = 1.8 v 97 ma three ports working (high-speed) v cc(5v0) = 5.0 v, v cc(i/o) = 3.3 v 130 ma v cc(5v0) = 3.3 v, v cc(i/o) = 3.3 v 117 ma v cc(5v0) = 5.0 v, v cc(i/o) = 1.8 v 122 ma v cc(5v0) = 3.3 v, v cc(i/o) = 1.8 v 117 ma
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 83 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 11. limiting values [1] class 2 according to jedec jesd22-a114 . [2] class iii following jedec jesd22-c101 . 12. recommended operating conditions [1] deep-sleep suspend mode. table 82. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v cc(i/o) input/output supply voltage - 0.5 +4.6 v v cc(5v0) supply voltage (5.0 v) - 0.5 +5.6 v v esd electrostatic discharge voltage human body model [1] pin 123, 124, 125, 126 - 1750 +1750 v all other pins - 2000 +2000 v charge device model [2] corner pins - 750 +750 v all other pins - 500 +500 v t stg storage temperature - 40 +125 c table 83. recommended operating conditions symbol parameter conditions min typ max unit v cc(i/o) input/output supply voltage v cc(i/o) = 3.3 v 3.0 3.3 3.6 v v cc(i/o) = 1.8 v 1.65 1.8 1.95 v v cc(5v0) supply voltage (5.0 v) 3.0 - 5.5 v t amb ambient temperature - 40 - +85 c i cc(susp) suspend supply current v cc(5v0) = 3.3 v [1] t amb = 25 c - 150 - m a t amb = 40 c - 300 - m a t amb = 85 c- 1- ma
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 84 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 13. static characteristics table 84. static characteristics: digital pins digital pins: a[17:1], data[31:0], cs_n, rd_n, wr_n, dack, dreq, irq, reset_n, suspend/wakeup_n, clkin, oc1_n, oc2_n, oc3_n. oc1_n, oc2_n and oc3_n are used as digital overcurrent pins; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit v cc(i/o) = 1.65 v to 1.95 v v ih high-level input voltage 1.2 - - v v il low-level input voltage - - 0.5 v v hys hysteresis voltage 0.4 - 0.7 v v ol low-level output voltage i ol = 3 ma - - 0.22 v cc(i/o) v v oh high-level output voltage 0.8 v cc(i/o) -- v i li input leakage current v i = 0 v to v cc(i/o) --1 m a c in input capacitance - 2.75 - pf v cc(i/o) = 3.0 v to 3.6 v v ih high-level input voltage 2.0 - - v v il low-level input voltage - - 0.8 v v hys hysteresis voltage 0.4 - 0.7 v v ol low-level output voltage i ol = 3 ma - - 0.4 v v oh high-level output voltage 2.4 - - v i li input leakage current v i = 0 v to v cc(i/o) --1 m a c i input capacitance - 2.75 - pf table 85. static characteristics: psw1_n, psw2_n, psw3_n v cc(i/o) = 1.65 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit v ol low-level output voltage i ol = 8 ma; pull-up to v cc(5v0) - - 0.4 v v oh high-level output voltage pull-up to v cc(i/o) -v cc(i/o) -v table 86. static characteristics: por t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit v trip(h) high-level trip voltage 1.0 1.2 1.4 v v trip(l) low-level trip voltage 0.95 1.1 1.3 v t porp internal por pulse width after reg1v8 > v trip(h) 200 - - ns table 87. static characteristics: ref5v v cc(i/o) = 1.65 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit v ih high-level input voltage - 5 - v
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 85 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller [1] the hs termination resistor is disabled, and the pull-up resistor is connected. only during reset, when both the hub and the device are capable of the high-speed operation. table 88. static characteristics: usb interface block (pins dm1 to dm3 and dp1 to dp3) v cc(i/o) = 1.65 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit input levels for high-speed v hssq high-speed squelch detection threshold voltage (differential signal amplitude) squelch detected - - 100 mv no squelch detected 150 - - mv v hsdsc high-speed disconnect detection threshold voltage (differential signal amplitude) disconnect detected 625 - - mv disconnect not detected - - 525 mv v hscm high-speed data signaling common mode voltage range (guideline for receiver) - 50 - +500 mv output levels for high-speed v hsoi high-speed idle level voltage - 10 - +10 mv v hsoh high-speed data signaling high-level voltage 360 - 440 mv v hsol high-speed data signaling low-level voltage - 10 - +10 mv v chirpj chirp j level (differential voltage) [1] 700 - 1100 mv v chirpk chirp k level (differential voltage) [1] - 900 - - 500 mv input levels for full-speed and low-speed v ih high-level input voltage 2.0 - - v v ihz high-level input voltage (?oating) for low-/full-speed 2.7 - 3.6 v v il low-level input voltage - - 0.8 v v di differential input sensitivity voltage | v dp - v dm | 0.2 - - v v cm differential common mode voltage range 0.8 - 2.5 v output levels for full-speed and low-speed v oh high-level output voltage 2.8 - 3.6 v v ol low-level output voltage 0 - 0.3 v v ose1 single-ended 1 (se1) output voltage 0.8 - - v v crs output signal crossover voltage 1.3 - 2.0 v
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 86 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 14. dynamic characteristics [1] recommended values for external capacitors when using a crystal are 22 pf to 27 pf. [2] recommended accuracy of the clock frequency is 50 10 - 6 for the crystal and oscillator. the oscillator used depends on v cc(i/o) . [1] this also serves as a high-speed termination. table 89. dynamic characteristics: system clock timing v cc(i/o) = 1.65 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit crystal oscillator f clk clock frequency crystal [1] [2] - 12 - mhz oscillator [2] - 12 - mhz external clock input t j external clock jitter - - 500 ps d duty cycle - 50 - % v i(xtal1) input voltage on pin xtal1 - v cc(i/o) -v t r rise time - - 3 ns t f fall time - - 3 ns table 90. dynamic characteristics: cpu interface block v cc(i/o) = 1.65 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit sr slew rate standard load 1 - 4 v/ns table 91. dynamic characteristics: high-speed source electrical characteristics v cc(i/o) = 1.65 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit driver characteristics t hsr rise time (10 % to 90 %) 500 - - ps t hsf fall time (10 % to 90 %) 500 - - ps z hsdrv driver output impedance (which also serves as high-speed termination) includes the r s resistor [1] 40.5 45 49.5 w clock timing t hsdrat high-speed data rate 479.76 - 480.24 mbit/s t hsfram microframe interval 124.9375 - 125.0625 m s t hsrfi consecutive microframe interval difference 1 - 8.33 ns
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 87 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller table 92. dynamic characteristics: full-speed source electrical characteristics v cc(i/o) = 1.65 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit driver characteristics t fr rise time c l = 50 pf; 10 % to 90 % of | v oh - v ol | 4 - 20 ns t ff fall time c l = 50 pf; 90 % to 10 % of | v oh - v ol | 4 - 20 ns t frfm differential rise and fall time matching 90 - 111.1 % data timing: see figure 13 t fdeop source jitter for differential transition to se0 transition full-speed timing - 2 - +5 ns t feopt source se0 interval of eop 160 - 175 ns t feopr receiver se0 interval of eop 82 - - ns t ldeop upstream facing port source jitter for differential transition to se0 transition low-speed timing - 40 - +100 ns t leopt source se0 interval of eop 1.25 - 1.5 m s t leopr receiver se0 interval of eop 670 - - ns t fst width of se0 interval during differential transition --14ns table 93. dynamic characteristics: low-speed source electrical characteristics v cc(i/o) = 1.65 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit driver characteristics t lr transition time: rise time 75 - 300 ns t lf transition time: fall time 75 - 300 ns t lrfm rise and fall time matching 90 - 125 % t period is the bit duration corresponding with the usb data rate. fig 13. usb source differential data-to-eop transition skew and eop width 004aaa929 t period differential data lines crossover point differential data to se0/eop skew n t period + t fdeop n t period + t ldeop source eop width: t feopt , t leopt receiver eop width: t feopr , t leopr crossover point extended +3.3 v 0 v
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 88 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 14.1 pio timing 14.1.1 register or memory write fig 14. register or memory write table 94. register or memory write t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter min max unit v cc(i/o) = 1.65 v to 1.95 v t h11 data hold after wr_n high 2 - ns t h21 cs_n hold after wr_n high 1 - ns t h31 address hold after wr_n high 2 - ns t w11 wr_n pulse width 17 - ns t su11 data set-up time before wr_n high 5 - ns t su21 address set-up time before wr_n high 5 - ns t su31 cs_n set-up time before wr_n high 5 - ns v cc(i/o) = 3.3 v to 3.6 v t h11 data hold after wr_n high 2 - ns t h21 cs_n hold after wr_n high 1 - ns t h31 address hold after wr_n high 2 - ns t w11 wr_n pulse width 17 - ns t su11 data set-up time before wr_n high 5 - ns t su21 address set-up time before wr_n high 5 - ns t su31 cs_n set-up time before wr_n high 5 - ns 004aaa527 address 01 a[17:1] address 02 cs_n data 01 data data 02 wr_n t h11 t h21 t h31 t w11 t su11 t su21 t su31
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 89 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 14.1.2 register read 14.1.3 register access fig 15. register read table 95. register read t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter min max unit v cc(i/o) = 1.65 v to 1.95 v t su12 address set-up time before rd_n low 0 - ns t su22 cs_n set-up time before rd_n low 0 - ns t w12 rd_n pulse width > t d12 -ns t d12 data valid time after rd_n low - 35 ns t d22 data valid time after rd_n high - 1 ns v cc(i/o) = 3.3 v to 3.6 v t su12 address set-up time before rd_n low 0 - ns t su22 cs_n set-up time before rd_n low 0 - ns t w12 rd_n pulse width > t d12 -ns t d12 data valid time after rd_n low - 22 ns t d22 data valid time after rd_n high - 1 ns 004aaa524 address 01 a[17:1] address 02 data cs_n rd_n t su12 t su22 t w12 t d12 t d22 fig 16. register access 004aaa983 wr_n rd_n cs_n t whrl t rhwl t rhrl t whwl
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 90 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller [1] for ehci operational registers, minimum value is 195 ns. 14.1.4 memory read table 96. register access t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter min max unit t whrl wr_n high to rd_n low time 25 [1] -ns t rhrl rd_n high to rd_n low time 25 [1] -ns t rhwl rd_n high to wr_n low time 25 - ns t whwl wr_n high to wr_n low time 25 [1] -ns fig 17. memory read table 97. memory read t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter min max unit v cc(i/o) = 1.65 v to 1.95 v t p13 initial pre-fetch time 90 - ns t cy13 memory rd_n cycle time 40 - ns t d13 data valid time after rd_n low - 31 ns t d23 data available time after rd_n high - 1 ns t w13 rd_n pulse width 32 - ns t su13 cs_n set-up time before rd_n low 0 - ns t su23 address set-up time before rd_n low 0 - ns v cc(i/o) = 3.3 v to 3.6 v t p13 initial pre-fetch time 90 - ns t cy13 memory rd_n cycle time 36 - ns t d13 data valid time after rd_n low - 20 ns 004aaa523 address = 33c a[17:1] address 2 address 1 address 3 data data data 2 data 1 data 3 cs_n wr_n rd_n t p13 t d13 t w13 t su23 t su13 t cy13 t d23
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 91 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 14.2 dma timing in the following sections: ? polarity of dack is active high ? polarity of dreq is active high. 14.2.1 single cycle: dma read t d23 data available time after rd_n high - 1 ns t w13 rd_n pulse width 21 - ns t su13 cs_n set-up time before rd_n low 0 - ns t su23 address set-up time before rd_n low 0 - ns table 97. memory read continued t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter min max unit fig 18. dma read (single cycle) table 98. dma read (single cycle) t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter min max unit v cc(i/o) = 1.65 v to 1.95 v t a14 dack assertion time after dreq assertion 0 - ns t a24 rd_n assertion time after dack assertion 0 - ns t d14 data valid time after rd_n assertion - 24 ns t w14 rd_n pulse width > t d14 -ns t a34 dreq de-assertion time after rd_n assertion - 29 ns t a44 dack de-assertion to next dreq assertion time - 56 ns t h14 data hold time after rd_n de-asserts - 5 ns v cc(i/o) = 3.3 v to 3.6 v t a14 dack assertion time after dreq assertion 0 - ns t a24 rd_n assertion time after dack assertion 0 - ns t d14 data valid time after rd_n assertion - 20 ns 004aaa530 data dreq dack rd_n t a14 t a24 t d14 t w14 t a44 t a34 t h14
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 92 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 14.2.2 single cycle: dma write t w14 rd_n pulse width > t d14 -ns t a34 dreq de-assertion time after rd_n assertion - 18 ns t a44 dack de-assertion to next dreq assertion time - 56 ns t h14 data hold time after rd_n de-asserts - 5 ns table 98. dma read (single cycle) continued t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter min max unit dreq and dack are active high. fig 19. dma write (single cycle) table 99. dma write (single cycle) t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter min max unit v cc(i/o) = 1.65 v to 1.95 v t a15 dack assertion time after dreq assertion 0 - ns t a25 wr_n assertion time after dack assertion 1 - ns t h15 data hold time after wr_n de-assertion 3 - ns t h25 dack hold time after wr_n de-assertion 0 - ns t su15 data set-up time before wr_n de-assertion 5.5 - ns t a35 dreq de-assertion time after wr_n assertion - 28 ns t cy15 last dack strobe de-assertion to next dreq assertion time -82ns t w15 wr_n pulse width 22 - ns v cc(i/o) = 3.3 v to 3.6 v t a15 dack assertion time after dreq assertion 0 - ns t a25 wr_n assertion time after dack assertion 1 - ns t h15 data hold time after wr_n de-assertion 2 - ns t h25 dack hold time after wr_n de-assertion 0 - ns t su15 data set-up time before wr_n de-assertion 5.5 - ns t a35 dreq de-assertion time after wr_n assertion - 16 ns t cy15 last dack strobe de-assertion to next dreq assertion time -82ns t w15 wr_n pulse width 22 - ns 004aaa525 data data data 1 dreq wr_n dack t a15 t a25 t h15 t h25 t su15 t a35 t cy15 t w15
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 93 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 14.2.3 multi-cycle: dma read dreq and dack are active high. fig 20. dma read (multi-cycle burst) table 100. dma read (multi-cycle burst) t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter min max unit v cc(i/o) = 1.65 v to 1.95 v t a16 dack assertion after dreq assertion time 0 - ns t a26 rd_n assertion after dack assertion time 0 - ns t d16 data valid time after rd_n assertion - 31 ns t w16 rd_n pulse width 38 - ns t cy16 read-to-read cycle time 46 - ns t a36 dreq de-assertion time after last burst rd_n de-assertion -30ns t a46 dack de-assertion to next dreq assertion time -82ns t h16 data hold time after rd_n de-asserts - 5 ns v cc(i/o) = 3.3 v to 3.6 v t a16 dack assertion after dreq assertion time 0 - ns t a26 rd_n assertion after dack assertion time 0 - ns t d16 data valid time after rd_n assertion - 16 ns t w16 rd_n pulse width 17 - ns t cy16 read-to-read cycle time 38 - ns t a36 dreq de-assertion time after last burst rd_n de-assertion -20ns t a46 dack de-assertion to next dreq assertion time -82ns t h16 data hold time after rd_n de-asserts - 5 ns dreq t a36 dack rd_n 004aaa531 data 0 data data n-1 data 1 data n t a16 t a26 t d16 t w16 t cy16 t a46 t h16
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 94 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 14.2.4 multi-cycle: dma write fig 21. dma write (multi-cycle burst) table 101. dma write (multi-cycle burst) t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter min max unit v cc(i/o) = 1.65 v to 1.95 v t cy17 dma write cycle time 51 - ns t su17 data set-up time before wr_n de-assertion 5 - ns t h17 data hold time after wr_n de-assertion 2 - ns t a17 dack assertion time after dreq assertion 0 - ns t a27 wr_n assertion time after dack assertion 2 - ns t a37 dreq de-assertion time at last strobe (wr_n) assertion -28ns t h27 dack hold time after wr_n de-assertion 0 - ns t a47 strobe de-assertion to next strobe assertion time 34 - ns t w17 wr_n pulse width 17 - ns t a57 dack de-assertion to next dreq assertion time - 82 ns v cc(i/o) = 3.3 v to 3.6 v t cy17 dma write cycle time 51 - ns t su17 data set-up time before wr_n de-assertion 5 - ns t h17 data hold time after wr_n de-assertion 2 - ns t a17 dack assertion time after dreq assertion 0 - ns t a27 wr_n assertion time after dack assertion 1 - ns t a37 dreq de-assertion time at last strobe (wr_n) assertion -16ns t h27 dack hold time after wr_n de-assertion 0 - ns t a47 strobe de-assertion to next strobe assertion time 34 - ns t w17 wr_n pulse width 17 - ns t a57 dack de-assertion to next dreq assertion time - 82 ns 004aaa526 data 1 data data n-1 data 2 data n wr_n dreq dack t cy17 t su17 t h17 t a17 t a27 t a37 t h27 t a47 t w17 t a57
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 95 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 15. package outline fig 22. package outline sot425-1 (lqfp128) unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.15 15.85 0.81 0.59 7 0 o o 0.12 0.2 0.1 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot425-1 136e28 ms-026 00-01-19 03-02-20 d (1) (1) (1) 20.1 19.9 h d 22.15 21.85 e z 0.81 0.59 d 0 5 10 mm scale b p e q e a 1 a l p detail x l (a ) 3 b c b p e h a 2 d h v m b d z d a z e e v m a x 102 103 y w m w m a max. 1.6 lqfp128: plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm sot425-1 65 64 38 39 1 128 pin 1 index
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 96 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 16. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 16.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 16.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 16.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 97 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 16.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 23 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 102 and 103 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 23 . table 102. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 103. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 98 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 17. appendix 17.1 errata added on 2009-04-23 17.1.1 problem description when the saf1760 is programmed to perform in?nite retries on not acknowledged (nak) in tokens , the saf1760 does not generate the retry in tokens on its own. according to the saf1760 data sheet, if register rl is programmed as zero, nakcnt is ignored. this means that irrespective of the value of nakcnt, the saf1760 must retry inde?nitely because there is no nakcnt to limit the number of retries for a nak in token. the saf1760 hardware, however, does not retry the nak in token. 17.1.2 implication after an in token is seen on the usb bus and is nak-ed by the downstream device, the saf1760 will not perform any automatic retry. instead an interrupt will be generated in the atl_irq bit of the hcinterrupt register (310h), and the software must refresh the in token proprietary transfer descriptor (ptd) for the retry to occur on the usb bus. this causes the software to constantly service this retry, unless the application instructs it to stop retrying. 17.1.3 workaround 17.1.3.1 software retry mechanism set program register rl = 1111b and nakcnt = 1111b. in this case, interrupt will be generated when nakcnt reaches zero and the software has to reload the transfer descriptor. msl: moisture sensitivity level fig 23. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 99 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 17.1.3.2 hardware retry mechanism set program register rl = 0000b, nakcnt = 0000b and cerr = 10b. in this case, interrupt will not be generated for naks and hardware will retry inde?nitely, until the device responds with a data or an ack. 17.2 errata added on 2009-04-23 17.2.1 problem description when at least two usb devices are simultaneously running, it is observed that sometimes the int corresponding to one of the usb devices stops occurring. this may be observed sometimes with usb-to-serial or usb-to-network devices. the problem is not noticed when only usb mass storage devices are running. 17.2.2 implication this issue is because of the clearing of the respective done map bit on reading the atl ptd done map register when an int is generated by another ptd completion, but is not found set on that read access. in this situation, the respective done map bit will remain reset and no further int will be asserted, so the data transfer corresponding to that usb device will stop. 17.2.3 workaround an sof int can be used instead of an atl int with polling on done bits. a time-out can be implemented and if a certain done bit is never set, veri?cation of the ptd completion can be done by reading ptd contents (valid bit). 17.3 errata added on 2009-04-23 17.3.1 problem description when a low-speed or full-speed device is attached, after some time, the low-speed or full-speed device suddenly gets disconnected. the following sequence is observed when the problem occurs: ? the hub class driver detects a change of port status on the problematic port (through the interrupt endpoint of the hub). ? when a get port status command is sent to the problematic port, the port enable bit of the port status is cleared. this indicates that a port error has occurred. however, the current connection status still indicates that a device is present on the port. ? the hub driver sends a port reset command because of the clearing of the port enable bit. this causes the disconnection of the attached device and its renumeration. ? before the hub driver detects the port status change, all active transfers on the problematic port are halted. ? low-speed or full-speed devices connected to other ports are not affected when the problem occurs. ? the problem occurs with low-speed or full-speed devices. ? when low-speed or full-speed devices are connected through a high-speed hub, the problem will not occur.
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 100 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller ? during testing, it is observed that the problem always occurs on the port on which the device was last attached. 17.3.2 implication the implication will be serious if the device is getting disconnected during the data transfer. 17.3.3 workaround the software workaround will check if a port has suddenly been disabled ( port enable bit cleared) when a device is still connected to the port. once it detects this condition, the software workaround will perform the necessary steps to re-enable the port and reschedule any halted transfer because of the error condition. the following actions are taken by the software once the error condition is detected: ? increment the count of the variable that keeps the number of times the ports have been force enabled. ? determine which active ptds (atl and intl) are scheduled to the affected port and suspend them. ? determine the speed of the device connected to the affected port. ? put the internal hub in force con?gure mode. ? force enable the affected port (this will set the port enable bit of the affected port to 1 again). ? remove the force enable on the affected port. remark: if the force enable is set, the particular port will always be enabled even if the device connected has been removed. ? put the internal hub back to normal mode (exit from the force con?gure mode). ? re-active all the suspended ptds. there are two conditions when the software workaround will be invoked and appropriate actions will be taken to determine if it truly is a problematic behavior (see section 17.3.3.1 , section 17.3.3.2 and section 17.3.3.3 ). 17.3.3.1 condition 1 condition 1 refers to the condition when port enable/disable change event is detected in the hub class driver. to determine and resolve the problematic condition, the following steps are taken: ? determine if the hub event has occurred on one of the internal hubs three ports and if the connected device is either full-speed or low-speed. ? determine if the port enable bit is cleared when a device is still connected on the port. ? ensure that the port has not been force enabled three consecutive times by checking the variable that keeps track of the number of times the port has been force enabled. ? otherwise, reset the port if it has been force enabled three consecutive times. ? invoke the software workaround. check the port status again to see if the port has recovered. see also section 17.3.3.3 .
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 101 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 17.3.3.2 condition 2 condition 2 refers to the condition when a halt occurs during ptd processing without other bus errors (that is, babble, transaction error). to determine and resolve the problematic condition, the following steps are taken: ? check the completion status once a ptd scheduled towards a full-speed or low-speed device and connected through the internal hub is completed. ? if the ptd has been completed successfully, clear the variable that keeps track of the number of the times the port has been force enabled. ? if the ptd has been completed with a halt condition, get the port status of the port on which it is connected to the internal hub. ? determine if the port enable bit is cleared when a device is still connected to the port. ? ensure that the port has not been force enabled three consecutive times by checking the variable that keeps track of the number of times the port has been force enabled. otherwise, reset the port if it has been force enabled three consecutive times. ? invoke the software workaround. see also section 17.3.3.3 . 17.3.3.3 remarks because of this erratum, keep-alive eop will not appear on the usb bus for more than 3 ms and the device will enter the suspend state. after implementing the above mentioned workaround, keep-alive eop will start and the device will wake up to continue the function. in rare cases, because of the device implementation, there is a possibility that the device may not accept further requests from the host after the workaround. in such cases, application must perform the following partial enumeration steps to make the device work: 1. port power off 2. port power on 3. get descriptor 4. set interface as saf1760 has individual port power control mechanism, above sequence will be effective if the full-speed or low-speed device is directly connected to saf1760 ports.
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 102 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 18. abbreviations table 104. abbreviations acronym description ack acknowledgment asic application-speci?c integrated circuit async asynchronous atl asynchronous transfer list atx analog transceiver bcd binary coded decimal cpu central processing unit cs complete split dsc digital still camera dma direct memory access dw double word ehci enhanced host controller interface emi electromagnetic interference eop end-of-packet eot end-of-transfer esr effective series resistance fifo first in, first out fls frame list size gpio general-purpose i/o hc host controller hs high-speed hw hardware ic integrated circuit id identi?cation iec international electrotechnical commission int interrupt i/o input and output irq interrupt request iso isochronous isr interrupt service routine itd isochronous transfer descriptor itl isochronous (iso) transfer list ls line status nak not acknowledged nyet not yet oc overcurrent ohci open host controller interface pci peripheral component interconnect pda personal digital assistant
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 103 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller [1] letter x became a synonym for crystal. 19. glossary bulk transfer one of the four usb transfer types. it is an aperiodic, large burst communication, typically used for a transfer, which works with any available bandwidth. a bulk transfer can also be delayed until more bandwidth becomes available. endpoint a uniquely addressable portion of an usb device that is the source or sink of information in a communication ?ow between the host and the device. lazyclock a slow clock frequency that is kept running while the chip is in suspend mode. microframe a 125 m s time base established on high-speed buses. pid packet id pie parallel interface engine pio programmed i/o pll phase-locked loop pmos positive-channel metal-oxide semiconductor por power-on reset porp power-on reset pulse pp port power ppc port power control ptd periodic transfer descriptor ptd proprietary transfer descriptor ram random access memory risc reduced instruction set computer r/s run/stop r/w read/write se0 single ended 0 se1 single ended 1 sitd split isochronous transfer descriptor sof start-of-frame sram static ram ss start split sw software td transfer descriptor tt transaction translator uhci universal host controller interface usb universal serial bus xosc crystal oscillator [1] table 104. abbreviations continued acronym description
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 104 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 20. references [1] universal serial bus speci?cation rev. 2.0 [2] enhanced host controller interface speci?cation for universal serial bus rev. 1.0 21. revision history table 105. revision history document id release date data sheet status change notice supersedes saf1760_1 20091109 product data sheet - -
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 105 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 22. legal information 22.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 22.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 22.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. export control this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. 22.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. 23. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 106 of 110 continued >> nxp semiconductors saf1760 embedded hi-speed usb host controller 24. tables table 1. ordering information . . . . . . . . . . . . . . . . . . . . .3 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 table 3. port connection scenarios . . . . . . . . . . . . . . . .14 table 4. memory address . . . . . . . . . . . . . . . . . . . . . . .16 table 5. using the irq mask and or irq mask or registers . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 6. hybrid mode . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 7. pin status in hybrid mode . . . . . . . . . . . . . . . .26 table 8. register overview . . . . . . . . . . . . . . . . . . . . . .28 table 9. caplength - capability length register (address 0000h) bit description . . . . . . . . . . . .29 table 10. hciversion - host controller interface version number register (address 0002h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .29 table 11. hcsparams - host controller structural parameters register (address 0004h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 12. hcsparams - host controller structural parameters register (address 0004h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 13. hccparams - host controller capability parameters register (address 0008h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 14. hccparams - host controller capability parameters register (address 0008h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 15. usbcmd - usb command register (address 0020h) bit allocation . . . . . . . . . . . . .32 table 16. usbcmd - usb command register (address 0020h) bit description . . . . . . . . . . . .32 table 17. usbsts - usb status register (address 0024h) bit allocation . . . . . . . . . . . . .33 table 18. usbsts - usb status register (address 0024h) bit description . . . . . . . . . . . .33 table 19. frindex - frame index register (address: 002ch) bit allocation . . . . . . . . . . . .34 table 20. frindex - frame index register (address: 002ch) bit description . . . . . . . . . . .34 table 21. configflag - con?gure flag register (address 0060h) bit allocation . . . . . . . . . . . . .35 table 22. configflag - con?gure flag register (address 0060h) bit description . . . . . . . . . . . .35 table 23. portsc1 - port status and control 1 register (address 0064h) bit allocation . . . . . . .36 table 24. portsc1 - port status and control 1 register (address 0064h) bit description . . . . .36 table 25. iso ptd done map register (address 0130h) bit description . . . . . . . . . . . .37 table 26. iso ptd skip map register (address 0134h) bit description . . . . . . . . . . . . 37 table 27. iso ptd last ptd register (address 0138h) bit description . . . . . . . . . . . . 37 table 28. int ptd done map register (address 0140h) bit description . . . . . . . . . . . . 38 table 29. int ptd skip map register (address 0144h) bit description . . . . . . . . . . . . 38 table 30. int ptd last ptd register (address 0148h) bit description . . . . . . . . . . . . 38 table 31. atl ptd done map register (address 0150h) bit description . . . . . . . . . . . . 39 table 32. atl ptd skip map register (address 0154h) bit description . . . . . . . . . . . . 39 table 33. atl ptd last ptd register (address 0158h) bit description . . . . . . . . . . . . 39 table 34. hw mode control - hardware mode control register (address 0300h) bit allocation . . . . . . 40 table 35. hw mode control - hardware mode control register (address 0300h) bit description . . . . . 40 table 36. chip id - chip identi?er register (address 0304h) bit description . . . . . . . . . . . . 41 table 37. scratch register (address 0308h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 38. sw reset - software reset register (address 030ch) bit allocation . . . . . . . . . . . . 42 table 39. sw reset - software reset register (address 030ch) bit description . . . . . . . . . . . 42 table 40. dma con?guration register (address 0330h) bit allocation . . . . . . . . . . . . . 43 table 41. dma con?guration register (address 0330h) bit description . . . . . . . . . . . . 43 table 42. buffer status register (address 0334h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 43. buffer status register (address 0334h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 44. atl done timeout register (address 0338h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 45. memory register (address 033ch) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 46. memory register (address 033ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 47. edge interrupt count register (address 0340h) bit allocation . . . . . . . . . . . . . 46 table 48. edge interrupt count register (address 0340h) bit description . . . . . . . . . . . . 46 table 49. dma start address register (address 0344h) bit allocation . . . . . . . . . . . . . 47
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 107 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller table 50. dma start address register (address 0344h) bit description . . . . . . . . . . . .47 table 51. power-down control register (address 0354h) bit allocation . . . . . . . . . . . . .48 table 52. power-down control register (address 0354h) bit description . . . . . . . . . . . .48 table 53. port 1 control register (address 0374h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .50 table 54. port 1 control register (address 0374h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .50 table 55. interrupt register (address 0310h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 56. interrupt register (address 0310h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 table 57. interrupt enable register (address 0314h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .53 table 58. interrupt enable register (address 0314h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .53 table 59. iso irq mask or register (address 0318h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .54 table 60. int irq mask or register (address 031ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . .54 table 61. atl irq mask or register (address 0320h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .55 table 62. iso irq mask and register (address 0324h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .55 table 63. int irq mask and register (address 0328h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .55 table 64. atl irq mask and register (address 032ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . .55 table 65. high-speed bulk in and out: bit allocation . . .58 table 66. high-speed bulk in and out: bit description .59 table 67. high-speed isochronous in and out: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 table 68. high-speed isochronous in and out: bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 table 69. high-speed interrupt in and out: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .66 table 70. high-speed interrupt in and out: bit description . . . . . . . . . . . . . . . . . . . . . . . . .67 table 71. microframe description . . . . . . . . . . . . . . . . . .69 table 72. start and complete split for bulk: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .70 table 73. start and complete split for bulk: bit description . . . . . . . . . . . . . . . . . . . . . . . . .71 table 74. se description . . . . . . . . . . . . . . . . . . . . . . . . .73 table 75. start and complete split for isochronous: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .74 table 76. start and complete split for isochronous: bit description . . . . . . . . . . . . . . . . . . . . . . . . .75 table 77. start and complete split for interrupt: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .78 table 78. start and complete split for interrupt: bit description . . . . . . . . . . . . . . . . . . . . . . . . .79 table 79. microframe description . . . . . . . . . . . . . . . . . .81 table 80. se description . . . . . . . . . . . . . . . . . . . . . . . . .81 table 81. power consumption . . . . . . . . . . . . . . . . . . . . .82 table 82. limiting values . . . . . . . . . . . . . . . . . . . . . . . . .83 table 83. recommended operating conditions . . . . . . . . 83 table 84. static characteristics: digital pins . . . . . . . . . . 84 table 85. static characteristics: psw1_n, psw2_n, psw3_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 86. static characteristics: por . . . . . . . . . . . . . . . 84 table 87. static characteristics: ref5v . . . . . . . . . . . . . 84 table 88. static characteristics: usb interface block (pins dm1 to dm3 and dp1 to dp3) . . . . . . . . 85 table 89. dynamic characteristics: system clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 90. dynamic characteristics: cpu interface block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 91. dynamic characteristics: high-speed source electrical characteristics . . . . . . . . . . . 86 table 92. dynamic characteristics: full-speed source electrical characteristics . . . . . . . . . . . 87 table 93. dynamic characteristics: low-speed source electrical characteristics . . . . . . . . . . . 87 table 94. register or memory write . . . . . . . . . . . . . . . . 88 table 95. register read . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 96. register access . . . . . . . . . . . . . . . . . . . . . . . . 90 table 97. memory read . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 98. dma read (single cycle) . . . . . . . . . . . . . . . . . 91 table 99. dma write (single cycle) . . . . . . . . . . . . . . . . . 92 table 100.dma read (multi-cycle burst) . . . . . . . . . . . . . . 93 table 101.dma write (multi-cycle burst) . . . . . . . . . . . . . 94 table 102.snpb eutectic process (from j-std-020c) . . . 97 table 103.lead-free process (from j-std-020c) . . . . . . 97 table 104.abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 105.revision history . . . . . . . . . . . . . . . . . . . . . . . 104
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 108 of 110 nxp semiconductors saf1760 embedded hi-speed usb host controller 25. figures fig 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 fig 2. pin con?guration (lqfp128); top view . . . . . . . . .5 fig 3. internal hub . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 fig 4. saf1760 clock scheme . . . . . . . . . . . . . . . . . . . .13 fig 5. memory segmentation and access block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 fig 6. adjusting analog overcurrent detection limit (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 fig 7. saf1760 power supply connection . . . . . . . . . . .25 fig 8. most commonly used power supply connection .25 fig 9. hybrid mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 fig 10. internal power-on reset timing . . . . . . . . . . . . . . .27 fig 11. clock with respect to the external power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . .27 fig 12. nextptd traversal rule. . . . . . . . . . . . . . . . . . . . .57 fig 13. usb source differential data-to-eop transition skew and eop width . . . . . . . . . . . . . .87 fig 14. register or memory write. . . . . . . . . . . . . . . . . . .88 fig 15. register read . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 fig 16. register access . . . . . . . . . . . . . . . . . . . . . . . . . .89 fig 17. memory read . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 fig 18. dma read (single cycle). . . . . . . . . . . . . . . . . . . .91 fig 19. dma write (single cycle) . . . . . . . . . . . . . . . . . . .92 fig 20. dma read (multi-cycle burst) . . . . . . . . . . . . . . . .93 fig 21. dma write (multi-cycle burst) . . . . . . . . . . . . . . . .94 fig 22. package outline sot425-1 (lqfp128) . . . . . . . .95 fig 23. temperature pro?les for large and small components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
saf1760_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 9 november 2009 109 of 110 continued >> nxp semiconductors saf1760 embedded hi-speed usb host controller 26. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3.1 examples of a multitude of possible applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 functional description . . . . . . . . . . . . . . . . . . 12 7.1 saf1760 internal architecture: advanced nxp slave host controller and hub . . . . . . . . . 12 7.1.1 internal clock scheme and port selection . . . . 13 7.2 host controller buffer memory block . . . . . . . . 14 7.2.1 general considerations. . . . . . . . . . . . . . . . . . 14 7.2.2 structure of the saf1760 host controller memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.3 accessing the saf1760 host controller memory: pio and dma . . . . . . . . . . . . . . . . . 17 7.3.1 pio mode access, memory read cycle . . . . . . 17 7.3.2 pio mode access, memory write cycle . . . . . 18 7.3.3 pio mode access, register read cycle . . . . . . 18 7.3.4 pio mode access, register write cycle . . . . . . 18 7.3.5 dma mode, read and write operations . . . . . . 18 7.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.5 phase-locked loop (pll) clock multiplier . . . 22 7.6 power management . . . . . . . . . . . . . . . . . . . . 22 7.7 overcurrent detection . . . . . . . . . . . . . . . . . . . 23 7.8 power supply . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.8.1 hybrid mode . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.9 power-on reset (por) . . . . . . . . . . . . . . . . . 27 8 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.1 ehci capability registers . . . . . . . . . . . . . . . . 29 8.1.1 caplength register. . . . . . . . . . . . . . . . . . . 29 8.1.2 hciversion register . . . . . . . . . . . . . . . . . . 29 8.1.3 hcsparams register . . . . . . . . . . . . . . . . . . 30 8.1.4 hccparams register . . . . . . . . . . . . . . . . . . 31 8.2 ehci operational registers . . . . . . . . . . . . . . . 32 8.2.1 usbcmd register . . . . . . . . . . . . . . . . . . . . . . 32 8.2.2 usbsts register . . . . . . . . . . . . . . . . . . . . . . 33 8.2.3 usbintr register . . . . . . . . . . . . . . . . . . . . . . 34 8.2.4 frindex register . . . . . . . . . . . . . . . . . . . . . . 34 8.2.5 configflag register . . . . . . . . . . . . . . . . . . 35 8.2.6 portsc1 register . . . . . . . . . . . . . . . . . . . . . 35 8.2.7 iso ptd done map register. . . . . . . . . . . . . . 37 8.2.8 iso ptd skip map register . . . . . . . . . . . . . . 37 8.2.9 iso ptd last ptd register . . . . . . . . . . . . . . 37 8.2.10 int ptd done map register. . . . . . . . . . . . . . 38 8.2.11 int ptd skip map register . . . . . . . . . . . . . . 38 8.2.12 int ptd last ptd register . . . . . . . . . . . . . . 38 8.2.13 atl ptd done map register . . . . . . . . . . . . . 39 8.2.14 atl ptd skip map register . . . . . . . . . . . . . . 39 8.2.15 atl ptd last ptd register . . . . . . . . . . . . . . 39 8.3 con?guration registers . . . . . . . . . . . . . . . . . . 40 8.3.1 hw mode control register . . . . . . . . . . . . . . . 40 8.3.2 chip id register . . . . . . . . . . . . . . . . . . . . . . . 41 8.3.3 scratch register . . . . . . . . . . . . . . . . . . . . . . . 41 8.3.4 sw reset register . . . . . . . . . . . . . . . . . . . . . 42 8.3.5 dma con?guration register . . . . . . . . . . . . . . 43 8.3.6 buffer status register . . . . . . . . . . . . . . . . . . . 44 8.3.7 atl done timeout register . . . . . . . . . . . . . . 45 8.3.8 memory register . . . . . . . . . . . . . . . . . . . . . . . 45 8.3.9 edge interrupt count register. . . . . . . . . . . . . 46 8.3.10 dma start address register . . . . . . . . . . . . . . 47 8.3.11 power-down control register . . . . . . . . . . . . . 48 8.3.12 port 1 control register . . . . . . . . . . . . . . . . . . 50 8.4 interrupt registers . . . . . . . . . . . . . . . . . . . . . . 51 8.4.1 interrupt register. . . . . . . . . . . . . . . . . . . . . . . 51 8.4.2 interrupt enable register. . . . . . . . . . . . . . . . . 53 8.4.3 iso irq mask or register. . . . . . . . . . . . . . . 54 8.4.4 int irq mask or register . . . . . . . . . . . . . . . 54 8.4.5 atl irq mask or register. . . . . . . . . . . . . . . 54 8.4.6 iso irq mask and register . . . . . . . . . . . . . 55 8.4.7 int irq mask and register. . . . . . . . . . . . . . 55 8.4.8 atl irq mask and register . . . . . . . . . . . . . 55 9 proprietary transfer descriptor (ptd). . . . . . 56 9.1 high-speed bulk in and out . . . . . . . . . . . . . 57 9.2 high-speed isochronous in and out . . . . . . 61 9.3 high-speed interrupt in and out . . . . . . . . . 65 9.4 start and complete split for bulk . . . . . . . . . . . 69 9.5 start and complete split for isochronous . . . . 73 9.6 start and complete split for interrupt . . . . . . . 77 10 power consumption . . . . . . . . . . . . . . . . . . . . 82 11 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 83 12 recommended operating conditions . . . . . . 83 13 static characteristics . . . . . . . . . . . . . . . . . . . 84 14 dynamic characteristics . . . . . . . . . . . . . . . . . 86 14.1 pio timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 14.1.1 register or memory write . . . . . . . . . . . . . . . . 88 14.1.2 register read . . . . . . . . . . . . . . . . . . . . . . . . . 89 14.1.3 register access . . . . . . . . . . . . . . . . . . . . . . . 89 14.1.4 memory read . . . . . . . . . . . . . . . . . . . . . . . . . 90
nxp semiconductors saf1760 embedded hi-speed usb host controller ? nxp b.v. 2009. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 9 november 2009 document identifier: saf1760_1 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 14.2 dma timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 14.2.1 single cycle: dma read . . . . . . . . . . . . . . . . . 91 14.2.2 single cycle: dma write . . . . . . . . . . . . . . . . . 92 14.2.3 multi-cycle: dma read. . . . . . . . . . . . . . . . . . . 93 14.2.4 multi-cycle: dma write . . . . . . . . . . . . . . . . . . 94 15 package outline . . . . . . . . . . . . . . . . . . . . . . . . 95 16 soldering of smd packages . . . . . . . . . . . . . . 96 16.1 introduction to soldering . . . . . . . . . . . . . . . . . 96 16.2 wave and re?ow soldering . . . . . . . . . . . . . . . 96 16.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 96 16.4 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 97 17 appendix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 17.1 errata added on 2009-04-23. . . . . . . . . . . . . . 98 17.1.1 problem description . . . . . . . . . . . . . . . . . . . . 98 17.1.2 implication. . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 17.1.3 workaround . . . . . . . . . . . . . . . . . . . . . . . . . . 98 17.1.3.1 software retry mechanism . . . . . . . . . . . . . . . 98 17.1.3.2 hardware retry mechanism. . . . . . . . . . . . . . . 99 17.2 errata added on 2009-04-23. . . . . . . . . . . . . . 99 17.2.1 problem description . . . . . . . . . . . . . . . . . . . . 99 17.2.2 implication. . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 17.2.3 workaround . . . . . . . . . . . . . . . . . . . . . . . . . . 99 17.3 errata added on 2009-04-23. . . . . . . . . . . . . . 99 17.3.1 problem description . . . . . . . . . . . . . . . . . . . . 99 17.3.2 implication. . . . . . . . . . . . . . . . . . . . . . . . . . . 100 17.3.3 workaround . . . . . . . . . . . . . . . . . . . . . . . . . 100 17.3.3.1 condition 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 100 17.3.3.2 condition 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 101 17.3.3.3 remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 18 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 102 19 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 20 references . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 21 revision history . . . . . . . . . . . . . . . . . . . . . . . 104 22 legal information. . . . . . . . . . . . . . . . . . . . . . 105 22.1 data sheet status . . . . . . . . . . . . . . . . . . . . . 105 22.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 22.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 105 22.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 105 23 contact information. . . . . . . . . . . . . . . . . . . . 105 24 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 25 figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 26 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

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